MPU Memory Management Unit
2-43
MPU Subsystem
2.7.10 Permission Access
Both instructions and data need access permission checks, but their respec-
tive access violations are handled differently. A data access error generates
a DABORT and stores the status, domain, and address in FSR and FAR. An
instruction fetch generates an IABORT only; it does not update FSR and FAR
as it is possible the aborted instruction is not executed (if it is branched
around). The IABORT flags the instruction as it enters the TI925T.
When the MMU is turned off, the physical address is output directly and no
memory access permission checks are performed.
Table 2–25. Interpreting Access Permission
Domain
AP
S
R
Supervisor
User
Description
x0
xx
x
x
No access
No access
Generates a domain fault
01
00
0
0
No access
No access
Generates a permission fault
01
00
1
0
Read only
No access
Supervisor read only permitted
01
00
0
1
Read only
Read only
Any write generates a permission fault.
01
00
1
1
Reserved
Reserved
Generates a permission fault
01
01
x
x
Read/write
No access
Access allowed only in supervisor mode.
†
01
10
x
x
Read/write
Read only
User writes cause a permission fault.
†
01
11
x
x
Read/write
Read/write
All accesses are allowed.
†
01
xx
1
1
Reserved
Reserved
Generates a permission fault
11
xx
x
x
Full access
Full access
No permission fault can be generated.
† In client mode, the combination S/R = 11 is reserved and generates a permission fault. Therefore, on these three lines, S/R can
only take the values 00, 01, or 10.
2.7.11 Fault Checking Sequence
The sequence by which the MMU checks for access faults is slightly different
for sections and pages. Figure 2–20 illustrates the sequence for both. The
following sections describe the conditions that generate each of the faults.