Register Map
13-42
13.2.17
DMA FIFO Data Register (DATA_DMA)
The DMA FIFO data register (DATA_DMA) is the entry point to write or to read
data into/from an endpoint used in a DMA transfer through DMA channel 0, 1,
or 2.
Table 13–18. DMA FIFO Data Register (DATA_DMA)
Bit
Name
Description
15–0
DATA_DMA
DMA FIFO data
13.2.17.1
DMA FIFO Data(DATA_DMA)
When an RX DMA request is active for a channel (only one active at a given
time), this register contains the data received by the core from USB host OUT
transaction using this channel. Data can be accessed by the main DMA con-
troller engine (read access) in response to the DMA request for the channel.
When a TX DMA request is active for a channel (only one active at a given
time), this register contains the data written by the main DMA controller engine
(write access) in response to a DMA request for the transmit channel to be sent
to the USB host during the next IN transaction.
It is possible for both an RX DMA request and a TX DMA request to be
active at the same time. In this case, the main DMA controller engine can
access both transmit endpoint and receive endpoint FIFO. A read
access to DATA_DMA register affects the endpoint that caused the RX
DMA request to be active, and a write access affects the endpoint that
caused the TX DMA request to be active.
The local host must not access this register directly; however, there is no
hardware mechanism to protect from such access. Do not attempt
access into this register during DMA request handling.
