Register Map
13-22
13.2.6 Receive FIFO Status Register (RXFSTAT)
The read-only receive FIFO status register (RXSTAT) tells how many bytes are
in the receive FIFO for the selected endpoint. A write to this register has no
effect. The local host cannot read this register if EP_Sel bit is not set for the
endpoint.
Note:
No receive FIFO status exists for the setup FIFO, because 8 bytes always
are expected.
Table 13–7. Receive FIFO Status Register (RXSTAT)
Bit
Name
Description
15–10
–
Reserved
9–0
RXF_Count
Receive FIFO byte count
13.2.6.1
Receive FIFO Byte Count (RXF_Count)
This 10-bit field indicates the number of bytes currently in the receive FIFO.
Value after local host or USB reset is low (all 10 bits).
13.2.7 System Configuration Register 1 (SYSCON1)
The read/write system configuration 1 register (SYSCON1) provides control
functions for power management and miscellaneous control for the core.
Table 13–8. System Configuration Register 1(SYSCON1)
Bit
Name
Description
15–9
–
Reserved
8
Cfg_Lock
Device configuration locked
7–5
–
Reserved
4
Nak_En
NAK enable
3
–
Reserved
2
Self_Pwr
Self-powered
1
SOFF_Dis
Shutoff disable
0
Pullup_En
External pullup enable
