UART/IrDA Modes of Operation
12-87
UART Devices
12.8.2.6
Decoder
After reset, RXD is high and the 4-bit counter is cleared (see Figure 12–16).
When a rising edge is detected on RXIR, RXD falls on the next rising edge of
16XCLK with sufficient setup time. RXD remains low for 16 cycles (16XCLK)
and then returns to high as required by the IrDA specification. As long as no
pulses (rising edges) are detected on the RXIR, RXD remains high.
The reception of RXIR input can be disabled with DIS_IR_RX bits of the
auxiliary control register (ACREG[5]).
Figure 12–16. IrDA Decoder Mechanism
RXD
1
2
4
5
6
3
7
8
10
11
12
9
13
14
16
15
16XCLK
RXIR
12.8.2.7
Address Checking
In SIR mode, only frames intended for the device are written to the RX FIFO,
if address checking has been enabled. This avoids receiving frames not meant
for this device in a multipoint infrared environment. You can program two frame
addresses the UART IrDA receives with the XON1/ADDR1 and XON2/ADDR2
registers.
Selecting address1 checking is done by setting EFR[0] to 1. Address2 check-
ing is done by setting EFR[1] to 1. Setting EFR[1:0] to 0 disables all address
checking operations. If both bits are set, then the incoming frame is checked
for both the private and public addresses.
If address checking is disabled, then all received frames are written into the
reception FIFO.
