Coprocessor 15
2-22
Table 2–12. Lockdown Operations
Function
Opcode_2
CRm
Data
Instruction
Read D-TLB lock
0b000
0b0000
Value
MRC p15, 0, Rd, c10, c0, 0
Write D-TLB lock
0b000
0b0000
Value
MCR p15, 0, Rd, c10, c0, 0
Read I-TLB lock
0b001
0b0000
Value
MRC p15, 0, Rd, c10, c0, 1
Write I-TLB lock
0b001
0b0000
Value
MCR p15, 0, Rd, c10, c0, 1
Figure 2–7. Format of the Lock-Down Registers
31
26
25
20
19
16
Base Value
Current Victim
UNP/SBZ
15
1
0
UNP/SBZ
P
Loading of the TLB is managed by a victim counter, which counts from the pro-
grammed base value up to 63. Therefore, some pages or sections can be
locked inside the TLB if loaded between the entry 0 and the entry pointed to
by the base value register.
Flush operations invalidate both locked and non-locked entries. An entry can
also be maintained in the TLB during a global flush if the preserved bit was set
during the loading of this entry in the TLB. A flush entry operation invalidates
a TLB entry regardless of its state (preserved/unpreserved).
The flush operation does not modify the base value register but reinitializes the
victim counter to the base value.
The following code sequence locks a page/section in entry 3:
{flush page/section from TLB}
MCR p15, 0, Rd, c10, c0, 1
Rd content indicates base value = 4, current victim = 3
MRC p15, 0, Rd, c7, c13, 1
Prefetch I-line with VA in Rd generates a miss TLB that loads entry 3 (victim
counter is automatically updated to 4).
