LCD Controller Registers
11-42
HSYNC/VSYNC Rise or Fall Programmability
This bit determines whether the HSYNC/VSYNC signals are driven on the ris-
ing or falling edge of the pixel clock (PHSVS_ON_OFF must be turned on first).
By default, the HSYNC/VSYNC signals are driven on the falling edge of the
pixel clock, and the LCD pixel data is driven on the rising edge of pixel clock.
However, if the invert pixel clock (IPC) bit is set to 1, then the HSYNC and
VSYNC signals are driven on the rising edge of the pixel clock and pixel data
is driven on the falling edge. By setting the PHSVS_RISE_FALL bit and enab-
ling it (PHSVS_ON_OFF = 1), you can control on which edge the signals are
driven.
The waveforms in Figure 11–17 show PHSVS_ON_OFF = 0 and IPC = 1 in
TFT mode.
Figure 11–17.
Signal Timing When PHSVS_ON_OFF = 0
Pixel 0
LCD.AC
IPC=1
LCD.VS
LCD.HS
LCD.P[15:0]
LCD.PCLK
