Coprocessor 15
2-10
2.6
Coprocessor 15
TI925T operation and configuration are controlled with coprocessor instruc-
tions, configuration pins, and the MMU translation tables. The coprocessor in-
structions manipulate on-chip registers, which control the configuration of the
cache memories, write buffer, MMU, and a number of other options described
in the following sections.
2.6.1
CP15 Access
The CP15 defines 16 registers. Table 2–3 shows the registers available for
reading and for writing. While most registers are used to control various opera-
tions, some, such as register 0, only provide information. MRC and MCR
instructions can access CP15 registers in privileged mode only. Figure 2–2
contains the instruction bit pattern of the MCR and MRC instructions.
Figure 2–2. MRC, MCR Bit Pattern
31
28
27
24
23
22
21
20
19
18
17
16
Cond
1110
Opcode_1
L
Crn
15
12
11
8
7
5
4
3
0
Rd
1111
Opcode_2
1
CRm
The CRn field specifies the coprocessor register to access. The CRm field and
opcode_2 fields specify a particular action when addressing some registers
or shadow registers. The TI925T takes the undefined instruction trap upon
executing CDP, LDC, STC, and unprivileged MCR/MRC instructions on CP15.
2.6.2
Register Descriptions
The following terms and abbreviations are used throughout the register
descriptions:
-
Unpredictable (UNP): Reading from such a location returns data of unpre-
dictable value. Writing to this location causes unpredictable behavior or
an unpredictable change in device configuration.
-
Undefined (UND): Any access to such registers makes TI925T take the
undefined instruction trap.
-
Should be zero (SBZ): All bits written to this field must be 0.
