MMC/SD Host Controller
7-167
MPU Public Peripherals
7.12.9.2
MMC DMA Transmit Mode
In a DMA block write operation (single or multiple):
-
The DMA TX request signal is asserted to its active level when the FIFO
level becomes less than the threshold set in AE_level after the block write
command has been set (write action into MMC_CMD).
-
The DMA TX request is deasserted to its inactive level when the system
DMA has written one single word into the FIFO.
Because the request lasts one 16-bit word write cycle, it is recommended that
the threshold level (AE_level) equal DMA burst size (n) minus 1. For instance,
if the system DMA is programmed to transfer one word write access, AE_level
must be set to 0.
In DMA mode, because a new DMA TX request can be generated after the first
read from the FIFO by the core, it is possible for the FIFO to hold a maximum
of two DMA transfers of n words minus one. Hence the maximum permitted
DMA transfer size is half the FIFO size.
The MMC/SD host controller does not generate a new DMA request until the
system DMA has written the N words corresponding to the previous DMA
request, even if the FIFO level is equal to or greater than the programmed
threshold.
Because each DMA transfer has equal size, it is necessary to have the total
data size of the transfer be a multiple of the DMA write access size
(max 16 words).
Summary:
DMA transfer size = n
≤
FIFO size/2
(max 16 16-bit words)
AE_level = n -1 (FIFO threshold level)
n = submultiple of total transfer size
Example: Multiple block write of 10 blocks of 512 bytes each. The DMA trans-
fer size n can be set to 10 words (20 bytes) and AE_level= 0x9. Then the write
transfer operation completes after 256 system DMA write requests.
The transmit FIFO does not underflow. If the FIFO gets empty, the MMC_clk
clock signal is momentarily stopped till the system DMA or the local host
performs a write access, which starts filling the FIFO.
