Texas Instruments OMAP5910, Technical Reference Manual

Page: 229 / 1209

Traffic Controller Memory Interface Registers
4-55 Memory Interface Traffic Controller
The endianism register (ENDIANISM) is used to control endianism conversion
in the DSP memory management unit endianism block.
Table 4–25. Endianism Register (ENDIANISM)
Bit Field Value Description Access
Reset
Value
31–2 Reserved Read is undefined. Writes must be zero. R All 0
1 SWAP 0 Byte swap (8 bits) R/W 0
1 Word swap (16 bits)
0 EN 0 Endianism conversion is disabled (default). R/W 0
1 Endianism is enabled.
Table 4–26. EMIF Fast Interface SDRAM Configuration Register 2
(EMIFF_SDRAM_CONFIG_2)
Bit Field Value Description Access
Reset
Value
31–2 Reserved Read is undefined. Writes must be zero. R All 0
1 RFRSH_
RST SDRAM self-refresh on warm reset. RFRSH_RST
determines what action the TC SDRAM controller
takes toward setting SDRAM to self-refresh mode
in the event of a warm system reset. R/W 1
0 SDRAM is not entered to self-refresh mode.
1 SDRAM is entered to self-refresh mode upon warm
system reset.
0 RFRSH_
STBY SDRAM self-refresh on standby. After the TC
receives an idle request from the clock generation
module, RFRSH_STBY determines what action the
TC SDRAM controller takes toward setting SDRAM
to self-refresh mode prior to acknowledging the idle
request. R/W 1
0 SDRAM enters self-refresh mode.
1 SDRAM enters self-refresh mode prior to the TC
acknowledging an idle request.