Traffic Controller Memory Interface Registers
4-50
Table 4–17. SDRAM Internal Organization (Continued)
Register Value
Memory Size
(M Bits)
Size Of Data Bus
Number Of
Banks
1010
16
2
†
1011
16
4
1100
256
8
2
†
1101
8
4
1110
16
2
†
1111
16
4
† Unavailable bank number (not supported). Do not use this setting.
Note:
Reset value = 0x0h.
Table 4–18. Frequency Range
ac Parameters
SDF0
(Cycles)
SDF1
(Cycles)
SDF2
(Cycles)
SDF3
(Cycles)
t
rc
9
5
3
2
t
ras
5
3
2
2
t
rp
3
2
2
2
t
rcd
3
2
2
2
t
rrd
†
2
2
2
2
t
dpl
(trwl)
‡
–
–
–
–
t
dal
–
–
–
–
t
rsc
2
2
2
–
† Write is never interrupted by precharge command directly.
‡ Neither read or write with auto-precharge is supported.
