Traffic Controller Memory Interface Registers
4-47
Memory Interface Traffic Controller
Table 4–15. Wait Cycles Insertion
RDWST
Number of Cycles Inserted
0
2
1
3
2
4
3
5
4
6
5
7
There is no automatic hardware adjustment of the programmed latencies
when the system clock frequency changes.
The following restrictions apply when synchronous burst read Intel protocol is
selected:
-
Only continuous burst mode is supported
-
Only sequential data access order is supported
-
Only 1 clock cycle data duration mode is supported (there is no gain to
support 2 clock cycle duration since FLASH.CLK may be divided).
Page crossing is supported in page mode ROM burst read.
In asynchronous read mode, FLASH.ADV is activated during one FLASH.CLK
cycle in order to ensure compatibility with burst flash.
Table 4–16. EMIF Fast Interface SDRAM Configuration Register 1
(EMIFF_SDRAM_CONFIG)
Bit
Field
Value
Description
Access
Reset
Value
31–28
Reserved
Read is undefined. Writes must be zero.
R
All 0
27
CLK
SDRAM clock disable. See section 4.3.3.6,
SDRAM Clock Disable, for details related to
disabling the SDRAM clock.
R/W
0
0
Clock is not disabled.
1
Clock is disabled.
CLK is one of the prerequisites to meet TC idle.
CLK must be set before the memory interface can
acknowledge a TC idle request.
