Traffic Controller Memory Interface Registers
4-45
Memory Interface Traffic Controller
The four EMIF slow chip-select configuration registers (see Table 4–13) are
used to select the protocols and timings to be used for handshake with devices
connected to CS0 - CS3 (corresponding to device pins FLASH.CS0 -
FLASH.CS3). Table 4–14 describes the memory types, and Table 4–15
describes the wait cycles insertion.
Table 4–13. EMIF Slow Chip-Select Configuration Registers
(EMIFS_CS0_CONFIG...EMIFS_CS3_CONFIG)
Bit
Field
Value
Description
Access
Reset
Value
31–22
Reserved
Read is undefined. Writes must be zero.
R
All 0
21
FL
Specifies how EMIFS handles addressing when
performing 32-bit writes to the OMAP5910 16-bit
data bus.
R/W
0
0
The address is incremented for the second 16-bit
access (default).
1
The address is not incremented for the second
16-bit access.
This bit is valid only when EMIFS is configured for
16-bit data bus width (BW = 0). This bit has no
effect for read operations.
20
BW
Specifies EMIFS data bus width.
R/W
0
16-bit bus. This is the appropriate setting for
OMAP5910.
1
Reserved. Do not use this setting on OMAP5910.
(BW bit reset value depends on the chip-select: For
CS0 and CS3, BW = 0; For CS1 and CS2, BW = 1.
If CS1 or CS2 is to be used, BW must first be
written to 0 since OMAP5910 only supports 16-bit
bus.)
19
Reserved
Read is undefined. Writes must be zero.
R
0
18:16
RDMODE
Read mode select (see Table 4–14)
R/W
000
15:12
PGWST/WELEN
For read accesses, number of wait states for page
mode ROM reads within a page. For write
accesses, the length of WE pulse duration.
R/W
1111
11:8
WRWST
Numbers of wait states for write operation
R/W
1111
