Memory Interfaces
4-28
4.3.3.3
SDRAM Mode and Extended Mode Register Initialization
To make SDRAM memory accessible, its internal mode register must first be
configured. The MRS register contains the protocol information used to com-
municate with the OMAP5910 device (burst size, latency, write burst, etc.).
The EMRS register enables certain low-power characteristics for the SDRAM.
-
Writing to the EMIF fast interface SDRAM MRS register (EMIFF_MRS)
automatically forces the generation of an MRS command on the pins of
the SDRAM interface. When the command is issued, the content of the
OMAP5910 MRS register is placed on the SDRAM address bus and
latched by the SDRAM into its internal MRS register.
-
OMAP5910 uses the same EMIF fast interface SDRAM MRS register,
combined with a control bit setting, to write EMRS commands to the
SDRAM. When the CONF_MOD_EMRS_CTRL bit field in the
MOD_CONF_CTRL_0 register is set, the OMAP configures SDRAM
banks to write out the EMIFF_MRS register as EMRS commands instead
of MRS commands.
-
Reading from the EMIF fast interface SDRAM MRS register does not
generate any external transactions.
Note:
The SDRAM requires 100
µ
s to stabilize after power up. Software is respon-
sible for performing the initial setup of SDRAM.
For more information see
Table 4–20, EMIF Fast Interface SDRAM MRS Register.
4.3.3.4
SDRAM Autorefresh Initialization
To increase SDRAM bus availability, it is preferable to subdivide the SDRAM
into smaller sections and then evenly distribute the refresh of each of these
subsections instead of performing a single autorefresh for the entire SDRAM.
The OMAP5910 device can support subdividing the autorefresh of the
SDRAM into bursts of 1, 4, or 8 rows. It is recommended to set this parameter
to 8 rows.
A 16-bit timer is used to track the interval between autorefresh burst requests
to the SDRAM. An autorefresh request is issued when the timer reaches a
user-defined value based on the following parameters:
-
SDRAM frequency
-
Refresh rate
-
Number of SDRAM rows
