Memory Interfaces
4-26
-
Dynamic priority
J
Dynamic priority uses high- and low-priority queues.
J
Each requestor, except the MPU, has a time-out register allocated to it
(see Time-Out Registers in Section 4.4). These registers hold the
number of clock cycles that a low-priority queue request has to wait
before it is moved from the low-priority queue to the high-priority
queue.
J
At reset, all requestors are initially in the low-priority queue and the
time-out registers are set to minimum value for each requestor. You
must program these registers before using dynamic priority.
J
The low-priority queue order is:
H
MPU
H
DSP
H
Local bus
H
DMA (all channels including LCD)
J
The high-priority queue order is:
H
DMA transfer involving LCD channel
H
DSP
H
Local bus
H
DMA transfer involving channels other than LCD channel
-
Fixed priority is a special case of dynamic priority. To create a fixed priority,
all time-out registers must have a value of 0. This way any request made
goes into the high-priority queue after one clock cycle. Then the high-
priority queue provides a fixed priority.
4.3.3.2
EMIFF Operation
The EMIFF controller can support up to two devices for up to 64M bytes of
memory. The following devices are supported:
-
256M-bit, 128M-bit, 64M-bit
-
2 or 4 banks for 64M-byte device
-
x8 or x16 data bus configurations
Table 4–7 shows the possible SDRAM configurations.
