MPU TI Peripheral Bus Bridges
2-66
2.10.2 TIPB Allocation
The MPU TIPBs are shared between the MPU and the DMA controller. A bus-
allocation module is provided to resolve conflicts and prioritize accesses.
The value written in the TIPB_BUS_ALLOC register defines the priority. If the
value is 0, the MPU memory interface has priority over the DMA controller. If
the value equals n (n from 1 to 7), the DMA controller has priority over the MPU
and it can perform n accesses before yielding to the MPU.
2.10.3 Access Factor and Time-Out
The MPU TIPB handles peripherals of varying speeds. To accommodate slow
peripherals, the access cycle (strobe period) is programmable.
The frequency of the MPU public and private TIPB strobe 1 and 0 are derived
from the traffic controller clock (CLKM3). For both TIPBs, you can use bits 3–0
(strobe 0) and bits 7–4 (strobe 1) of the TIPB control register (TIPB_CNTL) to
configure the access factor and consequently the strobe frequencies (as
shown in Table 2–58).
Table 2–58. Access Factor
Number of Wait States
(Access Factor)
Strobe Frequency
0
TC Clk/1
1
TC Clk/2
2
TC Clk/3
3
TC Clk/4
...
...
15
TC Clk/16
Each bridge in OMAP has two strobe lines, and a different division factor can
be programmed on each line.
A TIPB access time-out limits the maximum time a peripheral can stall the
processor. When starting a cycle on TIPB, the time-out counter is loaded with
this value (see TIPB_CNTL and ENHANCED_TIPB_CNTL registers). If the
current cycle is not finished when the counter reaches 0, the cycle is aborted
and an abort exception is generated to the MPU. The maximum value is 256
bridge clock cycles.
