Clock Generation and Reset Control Registers
15-80
The lock time register (LOCK_TIME) allows fixing the lock time when the APLL
is used. It represents the number of CLK (12-MHz or 13-MHz) periods required
to activate the APLL lock.
Table 15–39. Lock Time Register (LOCK_TIME)
Bit
Name
Description
Type
Reset
Value
15–0
LOCK_TIME
Indicates number of CLK (12-MHz or 13-MHz) periods to
wait for activate lock when APLL is used. The reset value
corresponds at a lock of 200
µ
s for a 12-MHz CLK.
R/W
0x960
APLL control register (APLL_CTRL_REG) allows the switch between the
APLL and the DPLL. It controls all the input of the APLL.
Table 15–40. APLL Control Register (APLL_CTRL_REG)
Bit
Name
Function
R/W
Reset Value
15:4
Reserved
Reserved. These bits should always be writ-
ten as 0.
R
0xx
3
SEL
Bit used to select correct divider so the APLL
can generate a 48-mHz clock from either a
12-mHz or 13-mHz reference source. Bit de-
faults to the 12-mHz reference setting.
0: Divide by 13 provides 1-mHz clock to APLL
for 48-mHz generation (if reference clock is
13-mHz)
1: Divide by 12 provides 1-mHz clock to APLL
for 48-mHz generation (if reference clock is
12-mHz)
R/W
0x1
2-1
RESERVED
Reserved. These bits should always be writ-
ten as 0.
R/W
0x0
0
APLL_NDPLL_SWITCH
It allows switch between APLL and DPLL.
When 0, use DPLL; when 1, use APLL. By
default, use DPLL.
R/W
0x0
