Clock Generation and Reset Control Registers
15-75
Clock Generation and System Reset Management
The counter high frequency MSB register (COUNTER_HIGH_FREQ_MSB_REG)
represents the upper value of the number of ticks from the high-frequency
clock during gauging time.
Table 15–30. Counter High Frequency MSB Register (COUNTER_HIGH_FREQ_MSB_REG)
Bit
Name
Type
Reset
Value
15–0
COUNTER_HIGH_FREQ_LSB
R
0x0000
The gauging control register (GAUGING_CTRL_REG) controls the gauging
activity. It start/stops it and selects the clock used as the high-frequency clock.
Table 15–31. Gauging Control Register (GAUGING_CTRL_REG)
Bit
Name
Value
Description
Type
Reset
Value
1
SELECT_HI_
FREQ_CLOCK
0
Use 12-MHz clock for high frequency clock
R/W
0
1
Reserved. Do not use this setting.
0
GAUGING_EN
0
Stop gauging
R/W
0
1
Enable gauging
The setup analog cell3 ULPD1 register (SETUP_ANA-
LOG_CELL3_ULPD1_REG) provides the number of 32-kHz clock periods
until the ULPD wakes up the device when a wake-up request is made. See
Figure 15–14 (page 15-37).
Table 15–32. Setup Analog Cell3 ULPD1 Register (SETUP_ANALOG_CELL3_ULPD1_REG)
Bit
Name
Type
Reset
Value
15–0
SETUP_ANALOG_CELL3
R/W
0x3FF
