Clock Generation and Reset Control Registers
15-65
Clock Generation and System Reset Management
Table 15–18. DSP Clock Control Register (DSP_CKCTL) – Offset Address: 0x00 (Continued)
Bit
Reset
Value
Type
Description
Value
Name
7
GPIOXO
Selects either a subfrequency issued from
CK_GEN2 or input reference clock (CLKIN) to
supply GPIO peripheral.
R/W
1
0
The DSP_GPIO_CK clock frequency is the input
reference clock.
1
DSP_GPIO_CK frequency is issued from CK_GEN2
and defined by the GPIODIV field value.
6–5
GPIODIV(1:0)
These read/write bits define prescaler value from
CK_GEN2 to the GPIO clock signal (GPIO_CK).
R/W
0
4–0
RESERVED
Reserved. These bits should always be written as 0.
Table 15–19 lists the selection for the DSP_GPIO_CK (GPIOXO = 1).
Table 15–19. GPIO_CK Selections
GPIODIV(1)
GPIODIV(0)
DSP_GPIO_CK Frequency
0
0
CK_GEN2/1
0
1
CK_GEN2/2
1
0
CK_GEN2/4
1
1
CK_GEN2/8
