Clock Generation and Reset Control Registers
15-51
Clock Generation and System Reset Management
Table 15–5. MPU Clock/Reset/Power Mode Control Registers – Base Address: FFFE:CE00
Register Name
Descriptions
R/W
Size
Offset
Reset
Value
ARM_CKCTL
Defines frequency for MPU, LCD, LCLB,
MPUPER clocks
R/W
16 bits
x00
0x0000 3000
ARM_IDLECT1
Enables and defines idle mode entry for
each clock domain
R/W
16 bits
x04
0x0000 0400
ARM_IDLECT2
Controls clock domains individually
R/W
16 bits
x08
0x0000 0100
ARM_EWUPCT
Delay from external device restore
power with reference to MPU clock
R/W
16 bits
x0C
0x0000 003F
ARM_RSTCT1
Initiates S/W reset to MPU and DSP
R/W
16 bits
x10
0x0000 0000
ARM_RSTCT2
Set PER_EN signal
R/W
16 bits
x14
0x0000 0000
ARM_SYSST
Contains system information such as
reset status flags, processor state
R/W
16 bits
x18
0x0000 0038
ARM_CKOUT2
Reserved
0x20
The MPU clock control register (ARM_CKCTL) defines the frequency for
ARM_CK, DSPMMU_CK, TC_CK, DSP_CK, LCD_CK, and MPUPER_CK.
Table 15–6. MPU Clock Control Register (ARM_CKCTL)
Bit
Name
Value
Description
Type
Reset
Value
15
RESERVED
Reading this bit gives an undefined value, and
writing to it has no effect.
14
ARM_INTHCK_SEL
This bit controls which clock is used for
ARM_INTH_CK.
R/W
0
0
TC_CK (this is default and must not be changed)
1
Reserved
Note:
If you select the fully synchronous mode, then it is your responsibility to program the divide-down bits so that ARMDIV,
DSPDIV DSPMMUDIV, and TCDIV are all equal. At reset, these divide-down bits are all defaulted to divide by 1.
In any mode, the DSPDIV and DSPMMUDIV must be set so that the DSPMMU_CK is either = to DSP_CK or
DSP_CK/2.
In synchronous scalable mode, you must make sure that the DSPMMUDIV and ARMDIV are greater than or equal to
TCDIV.
