Clock Generation
15-9
Clock Generation and System Reset Management
15.2.1 Clocking Schemes
The clock generator supports two clocking schemes to provide performance
flexibility and power-saving capabilities to the system. The clocking schemes
are programmable. Power-up mode defaults to fully synchronous mode.
Table 15–1 shows the clocking scheme selection, and Table 15–2 shows the
CLKM source selection.
Table 15–1. Clocking Scheme Selection
Clock_Select
Clocking Scheme
Remarks
000
Full synchronous
Default, bypass FIFO logic. TC=DSPMMU=MPU,
DSP = 1x or 2x of DSPMMU
001
Reserved
Do not use this setting
010
Synchronous scalable
Use FIFO logic between MPU and TC, DSP MMU and TC
Others
Reserved
Do not use this settings
Note:
In all the above cases, the frequency of the DSP can be 1x or 2x that of DSP MMU.
Table 15–2. CLKM Source Selection—Set via the MPU System Status Register
Clock
Select
Operating Mode
CLKM1
Input Clock
Source
CLKM2
Input Clock
Source
CLKM3
Input Clock
Source
Remarks
000
Fully synchronous
DPLL1/N
DPLL1/O
DPLL1/N
Notes 1, 2, 4
010
Synchronous scalable
DPLL1/M
DPLL1/N
DPLL1/O
Notes 3, 4
Notes:
1) If you select the fully synchronous mode, you must program the divide-down bits so that MPUDIV, DSPMMUDIV
and TCDIV are all equal. Further, DSPMMUDIV must be 1x or 1/2x that of DSPDIV.
2) CLKGEN1 = CLKGEN3 = DPLL1/N, CLKGEN2 = CLKGEN1 or 2*CLKGEN1 = DPLL1/O
3) M, N =< O, and O is a multiple (1, 2, 4, 8) of M, N.
4) The DSP MMU cannot run above the maximum speed of TC.
