Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 540 / 3738

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PRCM Register Manual
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Bits Field Name Description Type Reset
6:0 CORE_DPLL_EMU_DIV DPLL3 override divider factor (0 to 127) RW 0x00
Table 3-270. Register Call Summary for Register CM_CLKSEL2_EMU
PRCM Register Manual
• EMU_CM Register Summary : [0]
Table 3-271. CM_CLKSEL3_EMU
Address Offset 0x0000 0054
Physical Address 0x4800 5154 Instance EMU_CM
Description This register provides override controls over the PERIPHERAL DPLL.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED PERIPH_DPLL_EMU_MULT PERIPH_DPLL_EMU_DIV
RESERVED
OVERRIDE_ENABLE
Bits Field Name Description Type Reset
31:20 RESERVED Write 0s for future compatibility. Read returns 0. R 0x000
19 OVERRIDE_ENABLE This bit allows to enable or disable the emulation override RW 0x0
controls
0x0: The emulation override controls are disabled
0x1: The emulation override controls are enabled
18:8 PERIPH_DPLL_EMU_MULT DPLL4 override multiplier factor (0 to 2047) RW 0x000
7 RESERVED Write 0s for future compatibility. Read returns 0. R 0x0
6:0 PERIPH_DPLL_EMU_DIV DPLL4 override divider factor (0 to 127) RW 0x00
Table 3-272. Register Call Summary for Register CM_CLKSEL3_EMU
PRCM Register Manual
• EMU_CM Register Summary : [0]
3.8.1.13 Global_Reg_CM Registers
3.8.1.13.1 Global_Reg_CM Register Summary
Table 3-273. Global_Reg_CM Register Summary
Register Name Type Register Width Address Offset Physical Address Reset Type
(Bits)
CM_POLCTRL RW 32 0x0000 009C 0x4800 529C C
3.8.1.13.2 Global_Reg_CM Registers
540 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010
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