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PRCM Register Manual
Table 3-267. CM_CLKSTST_EMU
Address Offset
0x0000 004C
Physical Address
0x4800 514C
Instance
EMU_CM
Description
This register provides a status on the clock activity in the domain (depends on the selected source
clock).
Type
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
CLKACTIVITY_EMU
Bits
Field Name
Description
Type
Reset
31:1
RESERVED
Write 0s for future compatibility. Read returns 0.
R
0x00000000
0
CLKACTIVITY_EMU
Clock activity status (depends on the selected source
R
0x0
clock)
0x0: No domain clock activity
0x1: Domain clock is active
Table 3-268. Register Call Summary for Register CM_CLKSTST_EMU
PRCM Basic Programming Model
•
CM_CLKSTST_ <domain_name> (Clock State Status Register)
:
PRCM Register Manual
•
Table 3-269. CM_CLKSEL2_EMU
Address Offset
0x0000 0050
Physical Address
0x4800 5150
Instance
EMU_CM
Description
This register provides override controls over the DPLL3.
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
CORE_DPLL_EMU_MULT
CORE_DPLL_EMU_DIV
RESERVED
OVERRIDE_ENABLE
Bits
Field Name
Description
Type
Reset
31:20
RESERVED
Write 0s for future compatibility. Read returns 0.
R
0x000
19
OVERRIDE_ENABLE
This bit allows to enable or disable the emulation override
RW
0x0
controls
0x0: The emulation override controls are disabled
0x1: The emulation override controls are enabled
18:8
CORE_DPLL_EMU_MULT
DPLL3 override multiplier factor (0 to 2047)
RW
0x000
7
RESERVED
Write 0s for future compatibility. Read returns 0.
R
0x0
539
SWPU177N – December 2009 – Revised November 2010
Power, Reset, and Clock Management
Copyright © 2009–2010, Texas Instruments Incorporated
