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PRCM Basic Programming Model
3.6.1.3.2 MPU Interrupt Registers
3.6.1.3.2.1 PRM_IRQENABLE_MPU (MPU Interrupt Enable Register)
The MPU interrupt enable register allows independent masking/unmasking of each MPU internal interrupt
source.
NOTE:
If the following interrupts are enabled and the MPU power domain is idled, then when the
event occurs, the PRCM module sets the interrupt that wakes up the power domain:
•
DPLL1/DPLL2/DPLL3/DPLL4/DPLL5 recalibration event
•
Voltage controller errors
3.6.1.3.2.2 PRM_IRQSTATUS_MPU (MPU Interrupt Status Register)
The MPU interrupt status register provides the status of all PRCM internal events that can generate an
MPU interrupt. Software must read this register to identify the interrupt cause, and then clear the pending
interrupt by setting the corresponding bit to 1.
3.6.1.3.3 IVA2.2 Interrupt Event Sources
The IVA2.2 interrupt registers correspond to the interrupt sources connected to the interrupt line mapped
to the IVA2.2 interrupt controller.
Three events can activate this interrupt line:
•
An IVA2.2 peripheral group wake-up event
•
A force wake-up transition completion (IVA2 domain)
•
A required IVA2 DPLL recalibration
The PRM also interrupts IVA2.2 if the corresponding bit in the
register is set to
1.
The PRM triggers the interrupt line dedicated to the IVA2 processor when the MPU performs a force
wake-up transition on the IVA2 domain. This interrupt is triggered under the same conditions as that of the
MPU.
The PRM triggers an IVA2.2 interrupt if the DPLL recalibration flag is set and the corresponding interrupt
enable bit in the PRM_IRQENABLE_<processor_name> register is set to 1. The recalibration flag is set by
the DPLL and remains active if the DPLL is not reinitialized.
3.6.1.3.4 IVA2 Interrupt Registers
3.6.1.3.4.1 PRM_IRQENABLE_IVA2 (IVA2.2 Interrupt Enable Register)
The IVA2.2 interrupt enable register allows independent masking/unmasking of each of the three internal
interrupt sources.
NOTE:
If the IVA2 DPLL recalibration event interrupt is enabled and the IVA2 power domain is
idled, then when the event occurs, the PRCM module sets the interrupt, thus waking up the
power domain.
3.6.1.3.4.2 PRM_IRQSTATUS_IVA2 (IVA2.2 Interrupt Status Register)
The IVA2.2 interrupt status register provides the status of the three events that can generate an IVA2.2
interrupt. Software must read the register to identify the interrupt cause, and then clear the pending
interrupt by setting the corresponding bit to 1.
3.6.1.4
Event Generator Control Registers
For details about the event generator module, see the public ARM Cortex-A8 technical reference manual.
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SWPU177N – December 2009 – Revised November 2010
Power, Reset, and Clock Management
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