Public Version
www.ti.com
Preinitialization
Table 26-2. Mapping For Input Sources
Input Source
Mapping
Frequencies
Comment
Crystal quartz
sys_xtalin and sys_xtalout
12, 13, 16.8, or 19.2 MHz
Requires use of internal oscillator
Square clock
sys_xtalin
12, 13, 16.8, 19.2, 26, or
Internal oscillator is bypassed.
(1.8 CMOS signal)
(sys_xtalout unconnected)
38.4 MHz
Because sys_32k, sys_xtalin, and sys_xtalout have permanently assigned pin locations with no pad
configuration for these pins through a system control module (SCM) register, only one source input at a
time can be used.
26.2.2.2.2 Optional System Input Clock: sys_altclk
An additional clock can be provided through the sys_altclk input pin to supply internal peripherals, PLLs, a
precise clock for National Television System Committee (NTSC) standard (54 MHz), and a universal serial
bus (USB) full-speed (FS) controller (48 MHz). If not used as a clock input, this pin can be configured as a
general-purpose input/output (GPIO), using the SCM CONTROL.CONTROL_PADCONF_I2C3_SDA
register. As an example, to use the sys_altclk pin, the
CONTROL.CONTROL_PADCONF_I2C3_SDA[18:16] MUXMODE1 bit field must be set to 0x01.
26.2.2.2.3 Optional System Output Clock: sys_clkout1 and sys_clkout2
Two output clocks (sys_clkout1 and sys_clkout2 pins) are available:
•
sys_clkout1 can output the oscillator clock. Its OFF state polarity is programmable.
•
sys_clkout2 can output the system clock (12, 13, 16.8, 19.2, 26, or 38.4 MHz), the core clock (CORE
DPLL output), 96 MHz, or 54 MHz. sys_clkout2 can be divided by 2, 4, 8, or 16, and its OFF state
polarity is programmable.
CAUTION
Clock configurations depend on core voltage, and maximum clock frequencies
may not be applicable to production.
The clocks can be managed by software with the appropriate register in the power, reset, clock,
management (PRCM) module:
•
sys_clkout1 is managed using PRCM.PRM_CLKOUT_CTRL and PRCM.PRM_POLCTRL[2].
•
sys_clkout2 is managed using PRCM.CM_CLKOUT_CTRL and PRCM.CM_CLKSEL1_PLL[28:27].
26.2.2.3 Reset Configuration
The sys_nrespwron reset pin resets the entire chip during POR.
The sys_nreswarm reset pin resets the entire chip when the device is supplied and operating, except for
the following:
•
Part of synchronous dynamic RAM (SDRAM) controller (SDRC)
•
Part of IVA
•
Part of PRCM
•
Control module
•
Watchdog
•
32-kHz synchronization timer
•
DPLLs
•
SmartReflex™ modules
CAUTION
sys_nrespwron must be driven low during a power-up sequence.
3515
SWPU177N – December 2009 – Revised November 2010
Initialization
Copyright © 2009–2010, Texas Instruments Incorporated
