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MMC/SD/SDIO Register Manual
Bits
Field Name
Description
Type
Reset
6
MIT
MMC interrupt command (Only for MMC cards.)
RW
0
This bit must be set to 1, when the next write access to the
command register (MMCi.
) is for writing a MMC
interrupt command (CMD40) requiring the command timeout
detection to be disabled for the command response.
0x0:
Command timeout enabled
0x1:
Command timeout disabled
5
DW8
8-bit mode MMC select
RW
0
For SD/SDIO cards, this bit must be set to 0.
For MMC card, this bit must be set following a valid SWITCH
command (CMD6) with the correct value and extend CSD index
written in the argument. Prior to this command, the MMC card
configuration register (CSD and EXT_CSD) must be verified for
compliancy with MMC standard specification.
0x0:
1-bit or 4-bit Data width (mmci_dat[0] or mmci_dat[3:0]
used, MMC, SD cards)
0x1:
8-bit Data width (mmci_dat[7:0] used, MMC cards)
4
MODE
Mode select (All cards)
RW
0
These bits select the functional mode.
0x0:
Functional mode.
Transfers to the MMC/SD/SDIO cards follow the card
protocol. MMC clock is enabled. MMC/SD transfers are
operated under the control of the MMCi.
register.
0x1:
SYSTEST mode.
The signal pins are configured as general-purpose
input/output and the 1024-byte buffer is configured as a
stack memory accessible only by the local host or
system DMA. The pins retain their default type (input,
output or in-out). SYSTEST mode is operated under
the control of the SYSTEST register.
3
STR
Stream command (Only for MMC cards).
RW
0
This bit must be set to 1 only for the stream data transfers (read or
write) of the adtc commands.
Stream read is a class 1 command (CMD11:
READ_DAT_UNTIL_STOP).
Stream write is a class 3 command (CMD20:
WRITE_DAT_UNTIL_STOP).
0x0:
Block oriented data transfer.
0x1:
Stream oriented data transfer.
2
HR
Broadcast host response (Only for MMC cards).
RW
0
This register is used to force the host to generate a 48-bit
response for bc command type.
It can be used to terminate the interrupt mode by generating a
CMD40 response by the core. To have the host response to be
generated in open drain mode, the register
must be set to 1.
When MMCi.
[12] CEATA bit is set to 1 and
MMCi.
set to 0x00000000, when writing
0x00000000 into MMCi.
register, the host controller
performs a 'command completion signal disable' token (i.e.
mmci_cmd line held to '0' during 47 cycles followed by a 1).
0x0:
The host does not generate a 48-bit response instead
of a command.
0x1:
The host generates a 48-bit response instead of a
command or a command completion signal disable
token.
3433
SWPU177N – December 2009 – Revised November 2010
MMC/SD/SDIO Card Interface
Copyright © 2009–2010, Texas Instruments Incorporated