If the configuration set in the SDVS field is
not compliant with the supported voltage set
in the MMCHS_CAPA register, SDBP
returns to 0x0.
For initialization sequence, you should have
80 clock cycles in 1ms.
It means clock frequency should be
80 kHz
≤
Start
Write MMCi.MMCHS_HCTL register
(SDVS, SDBP, DTW) to configure the card voltage
value and power mode and dat bus width
SDBP = 0x1?
End
Yes
No
Read back the
MMCi.MMCHS_HCTL[8] SDBP bit
Set the MMCi.MMCHS_SYSCTL[0] ICE
bit to 0x1 to enable the internal clock
Configure the
MMCi.MMCHS_SYSCTL[15:6] CLKD
bit field
Read the MMCi.MMCHS_SYSCTL[1]
ICS bit
ICS = 0x1?
Yes
Clock is stable
Write the MMCi .MMCHS_SYSCONFIG
CLOCKACTIVITY, SIDLEMODE, and
AUTOIDLE fields to configure the
behavior of the module in idle mode
No
Write MMCi.MMCHS_CON register
to configure specific
data and command transfer
(OD, DW8, CEATA)
mmchs-028
Public Version
www.ti.com
MMC/SD/SDIO Basic Programming Model
Figure 24-34. MMC/SD/SDIO Controller Bus Configuration
24.5.2 Basic Operations for MMC/SD/SDIO Host Controller
The MMC/SD/SDIO host controller performs data transfers: data to card (referred to as write transfers)
and data from card (referred to as read transfers).
3399
SWPU177N – December 2009 – Revised November 2010
MMC/SD/SDIO Card Interface
Copyright © 2009–2010, Texas Instruments Incorporated