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High-Speed USB Host Subsystem
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rampup time is 10 x 2 ms = 20 ms.
•
[15:0] DR field (DeviceRemovable) = 0x0000: By default, no
nonremovable devices (that is, devices attached to any of the ports) are removable.
•
[31:16] PPCM field (PortPowerControlMask) = 0x0000: By default,
all ports are affected only by global power control.
22.2.4.1.3 UTMI Ports
The high-speed USB host controller supports N "downstream" ports, numbered from 1 through N. (In USB
terminology, port 0 is necessarily an "upstream" port, and because the host is on "top" of the USB
topological tree it has none). In the current implementation N = 3 (that is, available ports are 1, 2, 3).
The high-speed USB host controller is configured to be either in UTMI or in ULPI mode (see each port
configuration with the USBHOST.
[12] P3_ULPI_BYPASS,
USBHOST.
[11] P2_ULPI_BYPASS, and USBHOST.
P1_ULPI_BYPASS bits).
In UTMI mode (see USB 2.0 Transceiver Macrocell Interface specification Release
1.05
), all ports are in UTMI mode (that is, each port has its UTMI signal set broadcast
the "outgoing" packets - from the host to the peripherals) and gather the "incoming" ones (that is, from the
addressed peripheral to the host). ULPI signal sets are undefined/don't care on all ports.
In the device, the UTMI ports connect to the USBTLL module. The UTMI ports between the high-speed
USB host controller and the USBTLL module are on-chip and remain invisible.
22.2.4.1.4 ULPI Ports
The high-speed USB host controller supports N "downstream" ports, numbered from 1 through N. (In USB
terminology, port 0 is necessarily an "upstream" port, and because the host is on "top" of the USB
topological tree it has none). In the current implementation N = 3 (that is, available ports are 1, 2, 3).
The high-speed USB host controller is configured to be either in UTMI or in ULPI mode (see each port
configuration with the USBHOST.
[12] P3_ULPI_BYPASS,
USBHOST.
[11] P2_ULPI_BYPASS, and USBHOST.
P1_ULPI_BYPASS bits).
In ULPI mode , all ports are in ULPI mode (that is, each port has its ULPI signal set broadcast the
"outgoing" packets - from the host to the peripherals) and gather the "incoming" ones (that is, from the
addressed peripheral to the host). UTMI signal sets are undefined/don't care on all ports.
When in ULPI mode, the high-speed USB host controller is in charge of generating the (nominally
60-MHz) clock to the transceiver on the ULPI interface. This is called ULPI "input" clocking mode, because
the ULPI protocol is transceiver-centric. The opposite mode, "output mode" (that is, the host receives the
ULPI clock from the transceiver), is not supported and there is consequently no ULPI clock input.
In the device, the ULPI ports can only be connected directly to external transceivers. The USBTLL module
is bypassed. USB traffic can be monitored directly on the USB lines.
22.2.4.1.5 Port Status
The USB port status is given through the USBHOST.
[10:8] bit field. The default value
of the following bits is 1:
•
[8] P1_CONNECT_STATUS
•
[9] P2_CONNECT_STATUS
•
[10] P3_CONNECT_STATUS
3272
High-Speed USB Host Subsystem and High-Speed USB OTG Controller
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
