prcm-051
SYS_CLK
32K_FCLK
PRM
WKUP power domain
MUX
WKUP L4
interconnect
GPTIMER1
WDTIMER2
GPIO1
WKUP_L4_ICLK
GPT1_FCLK
WKUP_32K_FCLK
32-kHz
Sync Timer
Public Version
www.ti.com
PRCM Functional Description
Figure 3-55. WKUP Clock Signals
All clocks in the WKUP power domain are generated by the PRM. The functional clock GPT1_FCLK of
GPTIMER1 can be selected as SYS_CLK or 32K_FCLK. The 32-kHz sync timer, WDTIMER2, and GPIO1
receive 32K_FCLK as their functional clock. This is the low-frequency always-on clock.
The voltage controller module in the PRM receives SYS_CLK as its functional clock. The dedicated
SmartReflex I2C4 module implemented in the voltage controller uses the same functional clock
(SYS_CLK).
The PRM receives SYS_CLK as the L4 interface clock. For all other modules of the WKUP power domain,
the L4 interface clock WKUP_L4_ICLK is derived from SYS_CLK. Communication between the WKUP
power domain and CORE L4 interconnects is asynchronous.
3.5.3.4.1.10 PER Power Domain
shows the clock signals and their relationships in the PER power domain.
319
SWPU177N – December 2009 – Revised November 2010
Power, Reset, and Clock Management
Copyright © 2009–2010, Texas Instruments Incorporated
