Texas Instruments OMAP36 Series, Technical Reference Manual

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UART/IrDA/CIR Register Manual
Table 19-121. RXFIFO_LVL_REG
Address Offset 0x064
Physical Address Instance UART
See Table 19-39 to Table 19-40
Description Level of the RX FIFO
Type R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RXFIFO_LVL
Bits Field Name Description Type Reset
31:8 Reserved Read returns 0. R 0x000000
7:0 RXFIFO_LVL Shows the number of received bytes in the RX FIFO. R 0x00
Table 19-122. Register Call Summary for Register RXFIFO_LVL_REG
UART/IrDA/CIR Functional Description
• Register Access Modes : [0] [1] [2]
• UART/IrDA (SIR, MIR, FIR)/CIR Mode Selection : [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20]
UART/IrDA/CIR Register Manual
• UART/IrDA/CIR Register Summary : [21] [22]
Table 19-123. TXFIFO_LVL_REG
Address Offset 0x068
Physical Address Instance UART
See Table 19-39 to Table 19-40
Description Level of the TX FIFO
Type R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED TXFIFO_LVL
Bits Field Name Description Type Reset
31:8 Reserved Read returns 0x00. R 0x000000
7:0 TXFIFO_LVL Shows the number of received bytes in the TX FIFO. R 0x00
Table 19-124. Register Call Summary for Register TXFIFO_LVL_REG
UART/IrDA/CIR Functional Description
• Register Access Modes : [0] [1] [2]
• UART/IrDA (SIR, MIR, FIR)/CIR Mode Selection : [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20]
UART/IrDA/CIR Register Manual
• UART/IrDA/CIR Register Summary : [21] [22]
2971 SWPU177N – December 2009 – Revised November 2010 UART/IrDA/CIR
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