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Watchdog Timers
16.4.3.6 Start/Stop Sequence for WDTs (Using WDTi.WSPR Register)
To start/stop a WDT, access must be made through the start/stop register (WDTi.
) using a specific
sequence.
To disable the timer, follow this sequence:
1. Write 0xXXXX AAAA in WDTi.
2. Write 0xXXXX 5555 in WDTi.
To enable the timer, follow this sequence:
1. Write 0xXXXX BBBB in WDTi.
2. Write 0xXXXX 4444 in WDTi.
All other write sequences on WDTi.
have no effect on the start/stop feature of the module.
16.4.3.7 Modifying Timer Count/Load Values and Prescaler Setting
To modify the timer counter value (WDTi.
[4:2] PTV field), or load
value (the WDTi.
[31:0] TIMER_LOAD field), the WDT must be disabled by using the start/stop
sequence (the WDTi.
register).
After a write access, the load register value and prescaler ratio registers are updated immediately, but
new values are considered only after the next consecutive counter overflow or after a new trigger
command (WDTi.
16.4.3.8 Watchdog Counter Register Access Restriction (WDTi.WCRR Register)
Because the WDTi.
register is directly related to the timer counter value and is updated on the
timer clock (WDTi_FCLK), a 32-bit shadow register is implemented to read a coherent value of the
WDTi.
register. The shadow register is updated by a 16-bit LSB read command.
NOTE:
Although the L4 clock (WDTi_ICLK) is completely asynchronous with the timer clock
(WDTi_FCLK), some synchronization is done to ensure that the WDTi.
value is not
read while it is being incremented.
When 32-bit read access is performed, the shadow register is not updated. Read access is made directly
from the accessed register.
To ensure that a coherent value is read inside WDTi.
, the first read access is to the lower 16 bits
(offset = 0x08), followed by read access to the upper 16 bits (offset = 0x0A).
16.4.3.9 WDT Interrupt Generation
The WDT issues an overflow interrupt if this interrupt is enabled in the WDT interrupt enable register
(WDTi.
[0] OVF_IT_ENA = 1). When the overflow occurs, the interrupt status bit (the WDTi.
OVF_IT_FLAG bit) is set to 1. The output interrupt line (WDTi_IRQ) is asserted (active low) when both
status (OVF_IT_FLAG) and enable (OVF_IT_ENA) flags are set to 1; the order is not relevant. Writing 1 in
the enable bit (the status is already set at 1) also triggers the interrupt in the normal order (enable first,
status after). The pending interrupt event is cleared when the set status bit is overwritten by a value of 1
by a write command in the WTDi.
register. Reading the WTDi.
register and writing the value
back allows a fast acknowledge interrupt process.
NOTE:
Writing 0 in the WDTi.
[0] OVF_IT_FLAG bit has no effect on it.
Because the interrupt event is generated on the functional clock domain (WDTi_FCLK), during the
interrupt status register (WDTi.
) update, the two clock domains are resynchronized.
16.4.3.10 WDT Under Emulation
During emulation mode, the WDT can/cannot continue running, according on the value of the
WDTi.
[5] EMUFREE bit of the system configuration register (WDTi.
).
2753
SWPU177N – December 2009 – Revised November 2010
Timers
Copyright © 2009–2010, Texas Instruments Incorporated
