LOCK
STOP MODE
LOCK
SYS_32K
OSC_CLK
sys_nrespwron
SYS_CLK
Any warm reset source
EFUSE_RSTPWRON
sys_nreswarm_out
Global power on reset
Global warm reset
Registers warm reset
DPLL2, 4 & 5 state
DPLL 1 and DPLL3 state
DPLL2, 4 & 5 clock
DPLL1 and DPLL3 clock
PRM_RSTPWRON
CM_RSTPWRON_RET
Interconnect, memories,
interface clocks
CORE_RST
MPU_CLK
MPU_RST
L4_PER_CLK
PER_RST
Signal color-coding
PRCM input
PRCM output
Other
BYPASS
5
4
3
2
1
prcm-097
BYPASS
Public Version
www.ti.com
PRCM Functional Description
Figure 3-29. Warm Reset Sequence
The steps of a global warm reset sequence are as follows:
1. On assertion of the warm reset source:
•
The device reset manager resets part of the device by asserting the global warm reset.
•
The external warm reset (sys_nreswarm_out) is asserted.
271
SWPU177N – December 2009 – Revised November 2010
Power, Reset, and Clock Management
Copyright © 2009–2010, Texas Instruments Incorporated