Public Version
SCM Functional Description
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Table 13-52. Internal Signals Multiplexed on WKUPOBSMUX4
Pin Name
Observed Signal Name
WKUPOBSMU
Description
High State
Low State
X4 Field
CONTROL.
0] (dec)
hw_dbg4
(1)
CORE_OBSMUX4
0
Signal multiplexed by OBSMUX4.
–
–
PRCM_DPLL4_ALWON_F
1
Always-on functional clock of DPLL4.
–
–
CLK
PRCM_GPT9_ALWON_FC
2
Always-on functional clock of GP-Timer #9.
–
–
LK
PRCM_CAM_RST
3
Reset signal for CAM module.
Reset is not Reset is
active
active
Reserved for non-GP
4
Reserved for non-GP devices
Reset is not Reset is
devices
active
active
PRCM_MPU_domainIsOn
5
Indicates to the global Power Manager FSM
State is ON
State is not
that the MPU domain power state is ON.
ON
PRCM_mpu_domain_is_in
6
Indicates whether the MPU domain is active
Domain is
Domain is
active
or not.
inactive
active
PRCM_mpu_domain_is_ret
7
Indicates to the global Power Manager FSM
State is
State is not
ention
that the MPU domain power state is
RETENTIO
RETENTIO
RETENTION.
N
N
PRCM_mpu_domain_is_off
8
Indicates to the global Power Manager FSM
State is
State is not
that the MPU domain power state is OFF.
OFF
OFF
PRCM_SYS_CLKREQ_in
9
When SYS_CLKREQ is used as an input, it
–
–
is used to control the SYS.CLKOUT1 (and
the internal oscillator).
PRCM_vdd1_domain_go_o
10
Indicates a transition of the
domain to Transition
No
ff_mode
OFF_MODE.
initiated
transition
PRCM_MPU_SRAMRETO
11
SRAM retention on signal to MPU power
Retention is
Retention is
NIN[1]
domain (bit 1).
ON
OFF
PRCM_IVA2_SRAMAGOO
12
IVA2 array Powergood indication from
Power is
Power is
DOUT[2]
SRAM to PSCON (bit 2).
stable
not stable
PRCM_CORE_POWER_G
13
Indicates whether the CORE power
Power is
Power is
OOD[3]
switches status (bit 3).
stable
not stable
PRCM_CORE_SRAMRET
14
SRAM retention on signal to CORE power
Retention is
Retention is
ONIN[4]
domain (bit 4).
ON
OFF
PRCM_SGX_SRAMAONIN
15
SRAM array power control input (bit 2) for
Array is
Array is not
[0]
SGX power domain.
powered
powered
PRCM_CAM_POWER_GO
16
Indicates whether the CAM power switches
Power is
Power is
OD[2]
status (bit 2).
stable
not stable
PRCM_DPLL1_POWER_G
17
Indicates whether the DPLL1 power
Power is
Power is
OOD[0]
switches status (bit 0).
stable
not stable
PRCM_PER_POWER_RE
18
PER domain switch command for
Retention is
Retention is
T
power-retention.
ON
OFF
PRCM_FORCEACTIVECO
19
If asserted, the CORE domain is unable to
Sleep
Sleep
RE
start a sleep transition.
transition
transition
impossible
possible
PRCM_GPIO2_SWAKEUP
20
GPIO2 asserts this signal to initiate a
Transition
Wakeup
transition to WAKEUP mode.
initiated
conditions
not reached
Reserved
(31:21)
–
–
–
(1)
Mode 5 in MUXMODE1 field CONTROL.CONTROL_PADCONF_CAM_D1[18:16]
2508
System Control Module
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated