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SDMA Integration
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Hardware reset initializes all internal logic of the SDMA module, all global registers and some of the
per-channel registers, implemented in flip-flops. However, all remaining per-channel registers are
memory-based, and, therefore, are not reset (have undefined values). Thus, when programming a channel
for the first time, all bits that have undefined reset values must be configured before enabling the channel.
11.3.1.4 Power Management
The SDMA module provides three methods to reduce power consumption:
•
Internal clock gating (auto-idle)
•
Automatic standby mode
•
Idle mode
11.3.1.4.1 Internal Clock Gating (Auto-Idle)
The auto-idle power-saving mode is enabled or disabled through the
[0]
AUTOIDLE bit. When this mode is enabled and there is no activity on the interconnect interface, the
interface clock is disabled internally to the module to reduce power consumption. When there is new
activity on the interconnect interface, the interface clock is restarted without any latency penalty. After
reset, this mode is disabled by default. Enabling this mode is recommended to reduce power
consumption.
11.3.1.4.2 Automatic Standby Mode
The module can be configured to one of the following standby modes using the
[13:12] MIDLEMODE bit field:
•
Force-standby mode (MIDLEMODE = 0x0): The module goes into standby mode only when all the
DMA channels are disabled.
•
No-standby mode (MIDLEMODE = 0x1): The module never goes into standby mode.
•
Smart-standby mode (MIDLEMODE = 0x2): The module enters standby mode when:
–
All DMA channels are disabled
OR
–
No no-synchronous channels are enabled and if hardware synchronous channels are enabled, then
there should not be any hardware request asserted and there should not be any pending request in
DMA4 module
11.3.1.4.3 Idle Mode
The module can be configured using the
[3:2] SIDLEMODE bit field to one of
the following idle acknowledgement modes:
•
Force-idle mode (SIDLEMODE = 0x0): The module acknowledges unconditionally the idle request from
the PRCM module, regardless of its internal operations. This mode must be used carefully in this case
because it does not prevent the loss of data when the clocks are switched off.
•
No-idle mode (SIDLEMODE = 0x1): The module never acknowledges an idle request from the PRCM
module and is safe from a module point of view because it ensures that the clocks remain active.
However, it is not efficient to save power because it does not allow the PRCM output clocks to be shut
off and thus the power domain to be set to a lower power state.
•
Smart-idle mode (SIDLEMODE = 0x2): The module acknowledges the idle request, basing its decision
on its internal activity. Namely, the acknowledge signal is asserted when all the following conditions
are satisfied:
–
There is no non-synchronized channel enabled.
–
No DMA request input is asserted.
–
No pending request in the read and write port scheduler state machine.
–
All transactions are completed on all the DMA ports.
–
No interrupts are pending to be serviced.
2342
SDMA
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated