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SDRAM Controller (SDRC) Subsystem
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SDRC_SIDLEACK signal and the input clock frequency can be changed or stopped, depending on the
scenario. After the input clock is stable again, SDRC_IDLEREQ is de-asserted. The DLL then relocks and
the SDRC can be accessed normally. Putting the DLL in idle mode during the clock frequency change is
required because it cannot automatically relock. It might get into a non-functional state and a new manual
DLL configuration phase would then be required, with the risk of corrupting accesses in the mean time.
10.2.4 SDRC Subsystem Functional Description
The SMS optimizes the SDRAM memory usage to provide:
•
The QoS level required by each of the initiators in the system
•
A VRFB module (also called the 2D rotation engine) that minimizes the SDRAM page-miss penalty
when accessing rotated (that is, nonsequentially addressed) lines in a graphic frame buffer
10.2.4.1 SDRAM Memory Scheduler
The SMS module is split into the following subsystems:
•
L3 interconnect slave port
•
VRFB: Rotation engine (RE)
•
Configuration register file
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Request buffers
•
Arbitration logic
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SDRC interface: master port
•
Debug port
•
Response buffer
shows the top-level diagram of the SMS.
2236
Memory Subsystem
SWPU177N – December 2009 – Revised November 2010
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