sdrc-006
MUX26
MUX24
System address
System address
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1 0
Address mapping
Address mapping
b1 b0
b1 b0
b1 b0
Memory address
Memory address
11 10 9
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1 0
MUX27
System address
Address mapping
Memory address
MUX28
MUX23
MUX25
System address
System address
System address
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1 0
Address mapping
Address mapping
Address mapping
b1 b0
b1 b0
b1 b0
Memory address
Memory address
Memory address
12 11 10 9
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1 0
12 11 10 9
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1 0
12 11 10 9
8
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1 0
13 12 11 10 9
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1 0
13 12 11 10 9
8
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1 0
13−
14−
14−
bit row [12:0]
9
bit row [13:0]
9
bit row [13:0]
8
−
−
−
bit column [8:0]
bit column [8:0]
bit column [7:0]
8−
9−
9−
bit column [7:0]
bit column [8:0]
bit column [8:0]
15−
14−
15−
bit row [14:0]
bit row [13:0]
bit row [14:0]
13
13
13
12
14
14
Public Version
www.ti.com
SDRAM Controller (SDRC) Subsystem
Figure 10-46. SDRC SDR/DDR-SDRAM System Address Multiplexing Schemes (3 of 3)
10.2.3 SDRC Subsystem Integration
shows how the SMS and SDRC modules are integrated into the device and how they
interact with the PRCM module.
2233
SWPU177N – December 2009 – Revised November 2010
Memory Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated
