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L4 Interconnects
9.3
L4 Interconnects
9.3.1 Overview
To connect peripheral modules, the device uses four separate L4 interconnect structures. Although all L4
interconnects handle transfers with peripherals, the interconnects are in different power domains. The L4
interconnect is composed of the following:
•
L4-Core: Includes the majority of the peripherals and the configuration interface for L3 interconnect
system modules
•
L4-Per: Includes peripherals that do not need to be mapped in the CORE power domain
•
L4-Wakeup: Includes the peripherals attached to the WKUP power domain
•
L4-Emu: Includes emulation peripherals attached to the EMU power domain
The following are the main features of the L4 interconnects:
•
Single port to connect to L3 interconnect
–
L4-Core
–
L4-Per
•
Dual ports for the following:
–
L4-Emu to connect to the L3 interconnect and DAP
–
L4-Wakeup to connect to the L4-Core and L4-Emu
•
Single 32-bit initiator for the L3 port
•
Multitarget ports (one per target interface on the L4 interconnect)
•
8-, 16-, or 32-bit data, single, or burst transactions
•
Little-endian
•
Nonblocking with fair arbitration between threads
•
Peripherals are not burst-capable; the system initiators can address bursts to them, but the L4
interconnect breaks the bursts into single accesses.
•
Target interfaces: Fully synchronous or divided synchronous
•
Peak bandwidth of L4 interconnect is 1 MBps × L4 frequency in MHz per L4 thread (that is, 100 MBps,
when the L4 frequency is 100 MHz).
•
Latency: Three cycles on request, one cycle on response
•
Protection logic provides user-configurable access control to targets by each initiator:
–
Firewall in L4-Core protects the core and wake-up peripherals.
–
Firewall in L4-Per protects per peripherals.
–
Firewall in L4-Emu protects emulation and wake-up peripherals
NOTE:
L4-Wakeup has two input ports from L4-Core and L4-Emu. Therefore, wake-up peripherals
appear in two locations in the memory mapping. Normally, L4-Emu limits its access except
when debugging.
NOTE:
L4_CORE has four threads (maximum), L4_PER has four threads (maximum), and L4_EMU
and L4_WKUP have one thread.
shows an overview of the L4 interconnects and the periphreals attached to them.
2055
SWPU177N – December 2009 – Revised November 2010
Interconnect
Copyright © 2009–2010, Texas Instruments Incorporated
