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Introduction
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2.1
Introduction
The microprocessor unit (MPU) has a 32-bit address port, allowing it to handle a 4-GB space divided into
several regions, depending on the target type.
The memory map is composed of a memory space (general-purpose memory controller [GPMC],
synchronous dynamic random-access memory [SDRAM] controller [SDRC], etc.), register space (level 3
[L3] and level 4 [L4] interconnects), and dedicated spaces (image and video accelerator [IVA2.2]
subsystem, graphics accelerator (SGX), etc.), all of which are shared among the initiators (for example,
the MPU subsystem or the IVA2.2 subsystem).
The GPMC and SDRC are dedicated to memory connection. The GPMC is used for NOR/NAND flash and
SRAM memories. The SDRC is used for SDRAM memories, such as regular SDR-SDRAM (single data
rate), regular JEDEC DDR1 memory (double data rate), low-power SDR-SDRAM, and mobile
DDR-SDRAM. For more information, see
, Memory Subsystem.
The L3 interconnect allows the sharing of resources, such as peripherals and external or on-chip
memories, among all the initiators of the platform. The L4 interconnects control access to the peripherals.
Transfers between initiators and targets across the platform are physically conditioned by the chip
interconnect and can be logically conditioned by firewalls. For more information about the
intercommunication (L3 and L4 interconnects) and protection mechanisms implemented in the device, see
, Interconnect.
shows the interconnect of the device and the main modules and subsystems in the platform.
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Memory Mapping
SWPU177N – December 2009 – Revised November 2010
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