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L3 Interconnect
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9.2.2 L3 Interconnect Integration
9.2.2.1
Clocking, Reset, and Power-Management Scheme
9.2.2.1.1 Clocks
The power, reset, and clock management (PRCM) module provides the L3_ICLK as the main clock to the
L3 interconnect.
In addition to L3_ICLK, two additional sample signals are provided to module agents to allow internal
synchronization. The modules are as follows:
•
L4-Core
•
L4-Per
For more details on the L3 clock and its setting, see
, Power, Reset, and Clock Management.
Table 9-15. L3 Interconnect Clocks
Type
Name
Source
Description
Interface/functional
L3_ICLK
PRCM
Main clock for L3 interconnect
9.2.2.1.2 Resets
The L3 interconnect receives a single reset signal, CORE_RST, from the PRCM module. CORE_RST is
the reset signal to the core power domain. (For more details see Power, Reset, and Clock Management.)
When asserted, CORE_RST resets the L3 internal registers. There is no software reset for the L3
interconnect.
Table 9-16. L3 Interconnect Reset
Type
Reset Domain
Source
Description
Hardware
CORE_RST
PRCM
Asynchronous reset for the entire
interconnect
9.2.2.1.3 Power Domain
The L3 interconnect connects into the CORE power domain, which can dynamically switch between
supported OPPs. For more details on power voltage scaling, see Power, Reset, and Clock Management.
Table 9-17. L3 Interconnect Power Domain
Interconnect
Power Domain
L3 interconnect
CORE
9.2.2.1.4 Power Management
As part of the system-wide power-management scheme, the L3 interconnect enters an idle state at the
request of the PRCM module. (For more details, see
, Power, Reset, and Clock Management.)
The L3 interconnect is always in smart-idle mode; that is, it goes into idle state after receiving the request
from the PRCM module once all transfer requests are serviced. This functionality is handled by hardware.
The L3 interconnect sends an acknowledge signal back to the PRCM module when it enters the idle state.
2002
Interconnect
SWPU177N – December 2009 – Revised November 2010
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