Public Version
www.ti.com
Display Subsystem Overview
•
Reads data/status from the RFB to the L4 interconnect
–
RFB interface
•
8-/9-/12-/16-bit 8086-series parallel interface
•
Two programmable configurations for two devices connected to the RFBI module
–
Data formats
•
Programmable pixel modes (12-/16-/18-/24-BPP modes in RGB format)
•
Programmable output formats on one/multiple cycles per pixel (data from the display controller
and from the L4 interconnect)
–
Interconnect/FIFO
•
One slave port with DMA request and interconnect FIFO of 24x32-bit depth (for write access to
DSS.
register only)
•
One video port FIFO of 8 × 24-bit depth receiving data from the display controller
•
MIPI DSI
–
Transfer pixels and data received on the video port or L4 interconnect to the display through the
DSI DSI_PHY
–
The maximum resolution supported on the video port is XGA at 60 fps with 24-bit pixels (maximum
pixel clock of 67 MHz) for low voltage.
–
Supports video mode and command mode
–
Bidirectional data link support (only one data lane is used in reverse direction in command mode)
–
Supports up to two data-configurable lanes, in addition to the clock signaling (minimum of one data
link and maximum of two, depending on speed, signal integrity requirements, and number of
displays)
–
Maximum data rate of up to 900 Mbps per data pair
–
Data splitter for 2-data lane configuration
–
Error-correction code (ECC) and check-sum generation
–
Burst support for the video mode
–
RGB16, RGB18 packed and nonpacked, and RGB24 formats supported for video mode
–
Serial configuration port (SCP) for the DSI_PHY complex I/O and DSI PLL
–
Connection to the DSI_PHY complex I/O through PPI
–
Data interleaving support for one synchronous stream (video mode) from the display controller and
up to three interleaved asynchronous streams (command mode) from the interconnect concurrently
–
Data interleaving supports up to four interleaved asynchronous streams (command mode) from the
interconnect or video port when there is no video mode
–
MIPI DCS support (transparent to the protocol engine, no decoding and interpretation of the
information from and to the peripheral)
–
Supports selection between low-power state and HS mode between HS packet transfers
–
Generic data type (DT) support
NOTE:
The DSI pins are multiplexed with LCD parallel outputs.
•
Video encoder
–
NTSC/PAL encoder outputs with the following standards:
•
NTSC-J, M
•
PAL-B, D, G, H, I
•
PAL-M
–
CGMS-A as described in the CEA-608-x Standard.
–
Input data interface compatible with the following protocols:
•
24-bit input bus compatible with external sync
•
RGB 4:4:4
–
Dual output data 10-bit interface for two internal digital-to-analog converters (DACs) that support:
•
Composite video (CVBS)
•
Separate video (S-video)
1563
SWPU177N – December 2009 – Revised November 2010
Display Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated