Texas Instruments OMAP36 Series, Technical Reference Manual

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Camera ISP Register Manual
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Bits Field Name Description Type Reset
19 CCDC_LSC_PREFETCH_ERRO The prefetch error indicates when the gain table was read R/W/1to 0
R to slowly from SDRAM. Clr
READS:
0: event is false
1: event is true
WRITES
0: status bit unchanged
1: status bit reset
18 CCDC_LSC_PREFETCH_COMP Indicates current state of the prefetch buffer. R/W/1to 0
LETED READS: Clr
0: event is false
1: event is true
WRITES
0: status bit unchanged
1: status bit reset
17 CCDC_LSC_DONE The event is triggered when the internal state of LSC R/W/1to 0
toggles from BUSY to IDLE. Clr
READS:
0: event is false
1: event is true
WRITES
0: status bit unchanged
1: status bit reset
16 HIST_DONE_IRQ HIST module - processing done event. R/W/1to 0
READS: Clr
0: event is false
1: event is true
WRITES
0: status bit unchanged
1: status bit reset
15:14 RESERVED Write 0s for future compatibility. Read returns 0. R/W/1to 0
Clr
13 H3A_AWB_DONE_IRQ H3A module - auto exposure and auto white balance R/W/1to 0
processing done event. Clr
READS:
0: event is false
1: event is true
WRITES
0: status bit unchanged
1: status bit reset
12 H3A_AF_DONE_IRQ H3A module - autofocus processing done event. R/W/1to 0
READS: Clr
0: event is false
1: event is true
WRITES
0: status bit unchanged
1: status bit reset
11 CCDC_ERR_IRQ CCDC module - faulty pixel correction memory underflow R/W/1to 0
If event is true, one needs to clear the Clr
CCDC_FPC .FPERR bit first before clearing this bit.
READS:
0: event is false
1: event is true
WRITES
0: status bit unchanged
1: status bit reset
10 CCDC_VD2_IRQ CCDC module - programmable event 2 R/W/1to 0
READS: Clr
0: event is false
1: event is true
WRITES
0: status bit unchanged
1: status bit reset
1316 Camera Image Signal Processor SWPU177N – December 2009 – Revised November 2010
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