Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 1001 / 3738

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IVA2.2 Subsystem Register Manual
Table 5-519. WUGEN_PENDEVTCLR0
Address Offset 0x100
Physical address 0x01C2 1100 Instance IVA2.2 WUGEN
Description This register clears the masked pending interrupts (LSB):
Write 0: No effect
Write 1: Clears the corresponding mask bit in the
WUGEN_PENDEVT0 register
Reads always return 0
Type W
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PENDIRQ9 PENDIRQ8 PENDIRQ7 PENDIRQ6 PENDIRQ5 PENDIRQ4 PENDIRQ3 PENDIRQ2 PENDIRQ1 PENDIRQ0
PENDIRQ31 PENDIRQ30 PENDIRQ29 PENDIRQ28 PENDIRQ27 PENDIRQ26 PENDIRQ25 PENDIRQ24 PENDIRQ23 PENDIRQ22 PENDIRQ21 PENDIRQ20 PENDIRQ19 PENDIRQ18 PENDIRQ17 PENDIRQ16 PENDIRQ15 PENDIRQ14 PENDIRQ13 PENDIRQ12 PENDIRQ11 PENDIRQ10
Bits Field Name Description Type Reset
31 PENDIRQ31 Masked pending interrupt number 31 W 0
30 PENDIRQ30 Masked pending interrupt number 30 W 0
29 PENDIRQ29 Masked pending interrupt number 29 W 0
28 PENDIRQ28 Masked pending interrupt number 28 W 0
27 PENDIRQ27 Masked pending interrupt number 27 W 0
26 PENDIRQ26 Masked pending interrupt number 26 W 0
25 PENDIRQ25 Masked pending interrupt number 25 W 0
24 PENDIRQ24 Masked pending interrupt number 24 W 0
23 PENDIRQ23 Masked pending interrupt number 23 W 0
22 PENDIRQ22 Masked pending interrupt number 22 W 0
21 PENDIRQ21 Masked pending interrupt number 21 W 0
20 PENDIRQ20 Masked pending interrupt number 20 W 0
19 PENDIRQ19 Masked pending interrupt number 19 W 0
18 PENDIRQ18 Masked pending interrupt number 18 W 0
17 PENDIRQ17 Masked pending interrupt number 17 W 0
16 PENDIRQ16 Masked pending interrupt number 16 W 0
15 PENDIRQ15 Masked pending interrupt number 15 W 0
14 PENDIRQ14 Masked pending interrupt number 14 W 0
13 PENDIRQ13 Masked pending interrupt number 13 W 0
12 PENDIRQ12 Masked pending interrupt number 12 W 0
11 PENDIRQ11 Masked pending interrupt number 11 W 0
10 PENDIRQ10 Masked pending interrupt number 10 W 0
9 PENDIRQ9 Masked pending interrupt number 9 W 0
8 PENDIRQ8 Masked pending interrupt number 8 W 0
7 PENDIRQ7 Masked pending interrupt number 7 W 0
6 PENDIRQ6 Masked pending interrupt number 6 W 0
5 PENDIRQ5 Masked pending interrupt number 5 W 0
4 PENDIRQ4 Masked pending interrupt number 4 W 0
3 PENDIRQ3 Masked pending interrupt number 3 W 0
2 PENDIRQ2 Masked pending interrupt number 2 W 0
1 PENDIRQ1 Masked pending interrupt number 1 W 0
0 PENDIRQ0 Masked pending interrupt number 0 W 0
1001 SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem
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