USCI_A SPI Mode Registers
980
SLAU208Q – June 2008 – Revised March 2018
Copyright © 2008–2018, Texas Instruments Incorporated
Universal Serial Communication Interface – SPI Mode
37.4.3 UCAxBR0 Register
USCI_Ax Bit Rate Control Register 0
Figure 37-7. UCAxBR0 Register
7
6
5
4
3
2
1
0
UCBRx
rw
rw
rw
rw
rw
rw
rw
rw
Can be modified only when UCSWRST = 1.
Table 37-5. UCAxBR0 Register Description
Bit
Field
Type
Reset
Description
7-0
UCBRx
RW
undefine
d
Bit clock prescaler low byte. The 16-bit value of (U UCAxBR1 × 256)
forms the prescaler value UCBRx.
f
BitClock
= f
BRCLK
/ UCBRx
If UCBRx = 0, f
BitClock
= f
BRCLK
37.4.4 UCAxBR1 Register
USCI_Ax Bit Rate Control Register 1
Figure 37-8. UCAxBR1 Register
7
6
5
4
3
2
1
0
UCBRx
rw
rw
rw
rw
rw
rw
rw
rw
Can be modified only when UCSWRST = 1.
Table 37-6. UCAxBR1 Register Description
Bit
Field
Type
Reset
Description
7-0
UCBRx
RW
undefined
Bit clock prescaler high byte. The 16-bit value of (U UCAxBR1 × 256)
forms the prescaler value UCBRx.
f
BitClock
= f
BRCLK
/ UCBRx
If UCBRx = 0, f
BitClock
= f
BRCLK
37.4.5 UCAxMCTL Register
USCI_Ax Modulation Control Register
Figure 37-9. UCAxMCTL Register
7
6
5
4
3
2
1
0
Reserved
rw-0
rw-0
rw-0
rw-0
rw-0
rw-0
rw-0
rw-0
Table 37-7. UCAxMCTL Register Description
Bit
Field
Type
Reset
Description
7-0
Reserved
R
0h
Reserved. Always write as 0.