USCI_A UART Mode Registers
960
SLAU208Q – June 2008 – Revised March 2018
Copyright © 2008–2018, Texas Instruments Incorporated
Universal Serial Communication Interface – UART Mode
36.4.3 UCAxBR0 Register
USCI_Ax Baud Rate Control Register 0
Figure 36-14. UCAxBR0 Register
7
6
5
4
3
2
1
0
UCBRx
rw
rw
rw
rw
rw
rw
rw
rw
Can be modified only when UCSWRST = 1.
Table 36-9. UCAxBR0 Register Description
Bit
Field
Type
Reset
Description
7-0
UCBRx
RW
undefine
d
Low byte of clock prescaler setting of the baud-rate generator. The 16-bit value
of (U UCAxBR1 × 256) forms the prescaler value UCBRx.
36.4.4 UCAxBR1 Register
USCI_Ax Baud Rate Control Register 1
Figure 36-15. UCAxBR1 Register
7
6
5
4
3
2
1
0
UCBRx
rw
rw
rw
rw
rw
rw
rw
rw
Can be modified only when UCSWRST = 1.
Table 36-10. UCAxBR1 Register Description
Bit
Field
Type
Reset
Description
7-0
UCBRx
RW
undefined
High byte of clock prescaler setting of the baud-rate generator. The 16-bit value
of (U UCAxBR1 × 256) forms the prescaler value UCBRx.
36.4.5 UCAxMCTL Register
USCI_Ax Modulation Control Register
Figure 36-16. UCAxMCTL Register
7
6
5
4
3
2
1
0
UCBRFx
UCBRSx
UCOS16
rw-0
rw-0
rw-0
rw-0
rw-0
rw-0
rw-0
rw-0
Can be modified only when UCSWRST = 1.
Table 36-11. UCAxMCTL Register Description
Bit
Field
Type
Reset
Description
7-4
UCBRFx
RW
0h
First modulation stage select. These bits determine the modulation pattern for
BITCLK16 when UCOS16 = 1. Ignored with UCOS16 = 0.
shows the
modulation pattern.
3-1
UCBRSx
RW
0h
Second modulation stage select. These bits determine the modulation pattern for
BITCLK.
shows the modulation pattern.
0
UCOS16
RW
0h
Oversampling mode enabled
0b = Disabled
1b = Enabled