COMP_E Registers
930
SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
Comparator E (COMP_E) Module
35.3.6 CEIV Register (offset = 0Eh) [reset = 0000h]
Comparator_E Interrupt Vector Word Register
Figure 35-13. CEIV Register
15
14
13
12
11
10
9
8
CEIV
r0
r0
r0
r0
r0
r0
r0
r0
7
6
5
4
3
2
1
0
CEIV
r0
r0
r0
r0
r0
r-0
r-0
r0
Table 35-7. CEIV Register Description
Bit
Field
Type
Reset
Description
15-0
CEIV
R
0h
Comparator_E interrupt vector word register. The interrupt vector register reflects
only interrupt flags whose interrupt enable bit are set. Reading the CEIV register
clears the pending interrupt flag with the highest priority.
00h = No interrupt pending
02h = Interrupt Source: CEOUT interrupt; Interrupt Flag: CEIFG; Interrupt
Priority: Highest
04h = Interrupt Source: CEOUT interrupt inverted polarity; Interrupt Flag: CEIIFG
06h = Reserved
08h = Reserved
0Ah = Interrupt Source: Comparator ready interrupt; Interrupt Flag: CERDYIFG;
Interrupt Priority: Lowest