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SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
CPUX
Chapter 4
SLAU367P – October 2012 – Revised April 2020
CPUX
This chapter describes the extended MSP430X 16-bit RISC CPU (CPUX) with 1MB memory access, its
addressing modes, and instruction set.
NOTE:
The MSP430X CPUX implemented on this device family, formally called CPUXV2, has in
some cases, slightly different cycle counts from the MSP430X CPUX implemented on the
F2xx and F4xx families.
Topic
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Page
4.1
MSP430X CPU (CPUX) Introduction
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4.2
Interrupts
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4.3
CPU Registers
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4.4
Addressing Modes
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4.5
MSP430 and MSP430X Instructions
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4.6
Instruction Set Description
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