CPU Stop
Trigger
Blocks
MB0
MB1
MB2
MB3
MB4
MB5
MB6
MB7
CPU0
CPU1
&
0
Trigger Sequencer
"AND" Matrix− Combination Triggers
&
1
&
2
&
3
&
4
&
5
&
6
&
7
&
8
&
9
Start or Stop Cycle Counter
Start or Stop State Storage
OR
OR
OR
Embedded Emulation Module (EEM) Introduction
1019
SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
Embedded Emulation Module (EEM)
Figure 38-1. Large Implementation of EEM