Clock System Operation
3.2
Clock System Operation
After a PUC, the CS module default configuration is:
•
XT1 in low frequency (LF) mode (XTS = 0) is selected as the oscillator source for XT1CLK. XT1CLK is
selected for ACLK (SELA = {0}).
•
DCOCLK is selected for MCLK and SMCLK (SELM = SELS = {3}) and each are divided by 8 (DIVM =
DIVS = {3}).
•
XIN and XOUT pins are set to general-purpose I/Os and XT1 remains disabled until the I/O ports are
configured for XT1 operation.
•
When XT2 is available, XT2IN and XT2OUT pins are set to general-purpose I/Os and XT2 is disabled.
As previously stated, XT1 is selected by default, but XT1 is disabled. The crystal pins (XIN, XOUT) are
shared with general-purpose I/Os. To enable XT1, the PSEL bits associated with the crystal pins must be
set. When a 32768-Hz crystal is used for XT1CLK, the fault control logic immediately causes ACLK to be
sourced by the VLOCLK, because XT1 is not stable immediately (see
Status register control bits (SCG0, SCG1, OSCOFF, and CPUOFF) configure the device operating modes
and enable or disable portions of the clock system module (see the
System Resets, Interrupts, and
Operating Modes
chapter). Registers CSCTL0 through CSCTL6 configure the CS module.
The CS module can be configured or reconfigured by software at any time during program execution. The
CS control registers are password protected to prevent inadvertent access.
3.2.1 CS Module Features for Low-Power Applications
Conflicting requirements typically exist in battery-powered applications:
•
Low clock frequency for energy conservation and time keeping
•
High clock frequency for fast response times and fast burst processing capabilities
•
Clock stability over operating temperature and supply voltage
•
Low-cost applications with less-constrained clock accuracy requirements
The CS module addresses these conflicting requirements by allowing the user to select from the three
available clock signals: ACLK, MCLK, and SMCLK.
All three available clock signals can be sourced from any of the available clock sources (XT1CLK,
VLOCLK, DCOCLK, or XT2CLK), giving complete flexibility in the system clock configuration. A flexible
clock distribution and divider system is provided to fine-tune the individual clock requirements.
3.2.2 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
The internal VLO provides a typical frequency of 10 kHz (see the device-specific data sheet for
parameters) without requiring a crystal. The VLO provides for a low-cost ultralow-power clock source for
applications that do not require an accurate time base.
The VLO can be used to source ACLK, MCLK, or SMCLK (SELA = {1} or SELM = {1} or SELS = {1}).
3.2.3 XT1 Oscillator
The XT1 oscillator supports ultralow-current consumption using a 32768-Hz watch crystal in low-frequency
(LF) mode (XTS = 0). The watch crystal connects to the XIN and XOUT pins and requires external
capacitors on both terminals. These capacitors should be sized according to the crystal or resonator
specifications.
On devices that do not include the optional XT2 oscillator (see
), the XT1 oscillator also
supports high-speed crystals or resonators when in high-frequency (HF) mode (XTS = 1). The high-speed
crystal or resonator connects to XIN and XOUT and requires external capacitors on both terminals. These
capacitors should be sized according to the crystal or resonator specifications.
In XT1 LF or HF modes, different crystal or resonator ranges are supported by choosing the proper
XT1DRIVE settings. XT1 may be used with an external clock signal on the XIN pin in either LF or HF
mode by setting XT1BYPASS = 1. When used with an external signal, the external frequency must meet
the data sheet parameters for the chosen mode. XT1 is powered down when used in bypass mode.
73
SLAU272C – May 2011 – Revised November 2013
Clock System (CS)
Copyright © 2011–2013, Texas Instruments Incorporated