eUSCI_B Operation – I
2
C Mode
20.3.8.2 Automatic STOP Generation
When the eUSCI_B module is configured as a master, the byte counter can be used for automatic STOP
generation by setting the UCASTPx = 10. Before starting the transmission using UCTXSTT, the byte
counter threshold UCBxTBCNT must be set to the number of bytes that are to be transmitted or received.
After the number of bytes that are configured in UCBxTBCNT have been transmitted, the eUSCI_B
automatically generates a STOP condition.
UCBxTBCNT cannot be used if the user wants to transmit the slave address only without any data. In this
case, it is recommended to set UCTXSTT and UCTXSTP at the same time.
20.3.9 Multiple Slave Addresses
The eUSCI_B module supports two different ways of implementing multiple slave addresses at the same
time:
•
Hardware support for up to 4 different slave addresses, each with its own interrupt flag and DMA
trigger
•
Software support for up to 2
10
different slave addresses all sharing one interrupt
20.3.9.1 Multiple Slave Address Registers
The registers UCBxI2COA0, UCBxI2COA1, UCBxI2COA2, and UCBxI2COA3 contain four slave
addresses. Up to four address registers are compared against a received 7- or 10-bit address. Each slave
address must be activated by setting the UCAOEN bit in the corresponding UCBxI2COAx register.
Register UCBxI2COA3 has the highest priority if the address received on the bus matches more than one
of the slave address registers. The priority decreases with the index number of the address register, so
that UCBxI2COA0 in combination with the address mask has the lowest priority.
When one of the slave registers matches the 7- or 10-bit address seen on the bus, the address is
acknowledged. In the following the corresponding receive- or transmit-interrupt flag (UCTXIFGx or
UCRXIFGx) to the received address is updated. The state change interrupt flags are independent of the
address comparison result. They are updated according to the bus condition.
20.3.9.2 Address Mask Register
The address mask register can be used when the eUSCI_B is configured in slave or in multiple-master
mode. To activate this feature, at least one bit of the address mask in register UCBxADDMASK must be
cleared.
If the received address matches the own address in UCBxI2COA0 on all bit positions that are not masked
by UCBxADDMASK, the eUSCI_B module considers the received address as its own address. If
UCSWACK = 0, the module sends an acknowledge automatically. If UCSWACK = 1, the user software
must evaluate the received address in register UCBxADDRX after the UCSTTIFG is set. To acknowledge
the received address, the software must set UCTXACK to 1.
The eUSCI_B module also automatically acknowledges a slave address that is seen on the bus if the
address matches any of the enabled slave addresses defined in UCBxI2COA1 to UCBxI2COA3.
NOTE:
UCSWACK and slave-transmitter
If the user selects manual acknowledge of slave addresses, TXIFG is set if the slave is
addressed as a transmitter. If the software decides not to acknowledge the address, TXIFG0
must be reset.
20.3.10 Using the eUSCI_B Module in I
2
C Mode With Low-Power Modes
The eUSCI_B module provides automatic clock activation for use with low-power modes. When the
eUSCI_B clock source is inactive because the device is in a low-power mode, the eUSCI_B module
automatically activates it when needed, regardless of the control-bit settings for the clock source. The
clock remains active until the eUSCI_B module returns to its idle condition. After the eUSCI_B module
returns to the idle condition, control of the clock source reverts to the settings of its control bits.
549
SLAU272C – May 2011 – Revised November 2013
Enhanced Universal Serial Communication Interface (eUSCI) – I
2
C Mode
Copyright © 2011–2013, Texas Instruments Incorporated