(SVSMHCTL & SVSMHACE)) )
return 1; // SVSH affected configurations
}
if ((SVSMHCTL & SVMHE) && (!(SVSMHCTL & SVMHFP)) && (SVSMHCTL &
SVSMHACE))
return 1; // SVMH affected configurations
}
return 0; // SVS/M settings not affected by PMM15
}
}
2. If fast servicing of interrupts is required, add a 150us delay either in the interrupt
service routine or before entry into LPM3/LPM4.
PMM18
PMM Module
Category
Functional
Function
PMM supply overvoltage protection falsely triggers POR
Description
The PMM Supply Voltage Monitor (SVM) high side can be configured as overvoltage
protection (OVP) using the SVMHOVPE bit of SVSMHCTL register. In this mode a POR
should typically be triggered when DVCC reaches ~3.75V.
If the OVP feature of SVM high side is enabled going into LPM234, the SVM might trigger
at DVCC voltages below 3.6V (~3.5V) within a few ns after wake-up. This can falsely
cause an OVP-triggered POR. The OVP level is temperature sensitive during fail scenario
and decreases with higher temperature (85 degC ~3.2V).
Workaround
Use automatic control mode for high-side SVS & SVM (SVSMHCTL.SVSMHACE=1). The
SVM high side is inactive in LPM2, LPM3, and LPM4.
PMM20
PMM Module
Category
Functional
Function
Unexpected SVSL/SVML event during wakeup from LPM2/3/4 in fast wakeup mode
Description
If PMM low side is configured to operate in fast wakeup mode, during wakeup
from LPM2/3/4 the internal VCORE voltage can experience voltage drop below the
corresponding SVSL and SVML threshold (recommendation according to User's Guide)
leading to an unexpected SVSL/SVML event. Depending on PMM configuration, this
event triggers a POR or an interrupt.
Note
As soon the SVSL or the SVML is enabled in Normal performance mode the
device is in slow wakeup mode and this erratum does not apply. In addition, this
erratum has sporadic characteristic due to an internal asynchronous circuit. The
drop of Vcore does not have an impact on specified device performance.
Workaround
If SVSL or SVML is required for application (to observe external disruptive events at
Vcore pin) the slow wakeup mode has to be used to avoid unexpected SVSL/SVML
events. This is achieved if the SVSL or the SVML is configured in "Normal" performance
mode (not disabled and not in "Full" Performance Mode).
Advisory Descriptions
20
MSP430F6767 Microcontroller
SLAZ481AD – DECEMBER 2012 – REVISED MAY 2021
Copyright © 2021 Texas Instruments Incorporated
