Texas Instruments MSP430F6749 Manual Download

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Errata

MSP430F6749 Microcontroller

ABSTRACT

This document describes the known exceptions to the functional specifications (advisories).

Table of Contents

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2 Preprogrammed Software Advisories

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3 Debug Only Advisories

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4 Fixed by Compiler Advisories

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5 Nomenclature, Package Symbolization, and Revision Identification

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5.1 Device Nomenclature.........................................................................................................................................................

5.2 Package Markings..............................................................................................................................................................

5.3 Memory-Mapped Hardware Revision (TLV Structure).......................................................................................................

6 Advisory Descriptions

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7 Revision History

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Table of Contents

SLAZ484AD – DECEMBER 2012 – REVISED MAY 2021

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MSP430F6749 Microcontroller

Summary of Contents for MSP430F6749

Page 1: ...dvisories 3 4 Fixed by Compiler Advisories 3 5 Nomenclature Package Symbolization and Revision Identification 4 5 1 Device Nomenclature 4 5 2 Package Markings 4 5 3 Memory Mapped Hardware Revision TLV Structure 5 6 Advisory Descriptions 6 7 Revision History 26 www ti com Table of Contents SLAZ484AD DECEMBER 2012 REVISED MAY 2021 Submit Document Feedback MSP430F6749 Microcontroller 1 Copyright 2021...

Page 2: ... DMA10 LCDB6 PMM11 PMM12 PMM14 PMM15 PMM18 PMM20 PMM26 PORT15 PORT19 PORT26 RTC8 SD3 SYS16 UCS11 USCI36 USCI37 USCI41 USCI42 USCI47 USCI50 2 Preprogrammed Software Advisories Advisories that affect factory programmed software The check mark indicates that the issue is present in the specified revision Functional Advisories www ti com 2 MSP430F6749 Microcontroller SLAZ484AD DECEMBER 2012 REVISED MA...

Page 3: ...ision Errata Number Rev A CPU21 CPU22 CPU40 Refer to the following MSP430 compiler documentation for more details about the CPU bugs workarounds TI MSP430 Compiler Tools Code Composer Studio IDE MSP430 Optimizing C C Compiler Check the silicon_errata option MSP430 Assembly Language Tools MSP430 GNU Compiler MSP430 GCC MSP430 GCC Options Check msilicon errata and msilicon errata warn options MSP430...

Page 4: ...Fully qualified development support product XMS devices and X development support tools are shipped against the following disclaimer Developmental product is intended for internal evaluation purposes MSP devices have been characterized fully and the quality and reliability of the device have been demonstrated fully TI s standard warranty applies Predictions show that prototype devices XMS have a g...

Page 5: ...on how to locate the TLV structure and read out the HW_ID can be found in the device User s Guide www ti com Nomenclature Package Symbolization and Revision Identification SLAZ484AD DECEMBER 2012 REVISED MAY 2021 Submit Document Feedback MSP430F6749 Microcontroller 5 Copyright 2021 Texas Instruments Incorporated ...

Page 6: ...el repeat sequence of channels ADC12CTL1 ADC12CONSEQx In addition the timer overflow flag cannot be used to detect an overflow ADC12IFGR2 ADC12TOVIFG Workaround 1 For manual trigger mode ADC12CTL0 ADC12SC ensure each ADC conversion is completed by first checking ADC12CTL1 ADC12BUSY bit before starting a new conversion 2 For timer trigger mode ADC12CTL1 ADC12SHP ensure the timer period is greater t...

Page 7: ...not switch back to DVCC after DVCC ramps back up again Similarly when the system is running with the AUXVCC2 supply after DVCC AVCC is lost if the AUXVCC2 voltage goes lower than SVSH setting for POR and above BORH level the system can not switch back to DVCC after DVCC ramps back up again Workaround When the system is running with the AUXVCC1 supply use SVMH to monitor AUXVCC1 voltage When AUXVCC...

Page 8: ... applicable for AUXVCC2 of up to maximum voltage 3 58V while a lower SVSMRRL setting can be selected if a lower voltage e g 3 3V is expected on AUXVCC2 Or Connect all 3 supplies via 3 external diodes to DVCC and realize the switching externally without using the internal AUXPMM switches See application report Implementation of a Three Phase Electronic Watt Hour Meter Using the MSP430F471xx for det...

Page 9: ...least one of the following 1 Output inversion is disabled CECTL CEOUTPOL 0 OR 2 Change pin configuration from CEOUT to GPIO with output low CPU21 CPU Module Category Compiler Fixed Function Using POPM instruction on Status register may result in device hang up Description When an active interrupt service request is pending and the POPM instruction is used to set the Status Register SR and initiate...

Page 10: ...r Studio v4 0 x or later User is required to add the compiler or assembler flag option below silicon_errata CPU22 MSP430 GNU Compiler MSP430 GCC MSP430 GCC 4 9 build 167 or later CPU36 CPU Module Category Functional Function PC corruption when single stepping through flash erase Description When single stepping over code that initiates an INFOD Flash memory erase the program counter is corrupted W...

Page 11: ...struction is 0X40h or 0X50h where X don t care which could either be an instruction opcode for instructions like RRCM RRAM RLAM RRUM with PC as destination register or a data section const data in flash memory or data variable in RAM then the PC value is auto incremented by 2 after the jump instruction is executed therefore branching to a wrong address location in code and leading to wrong program...

Page 12: ...SFRIE1 VMAIE if it is enabled This issue occurs if the POPM assembly instruction is performed up to the top of the STACK Workaround If the user is utilizing C they will not be impacted by this issue All TI IAR GCC pre built libraries are not impacted by this bug To ensure that POPM is never executed up to the memory border of the STACK when using assembly it is recommended to either 1 Initialize t...

Page 13: ...8 bytes are affected In free running mode the last 4 bytes are affected Workaround Edit the linker command file to make the last 4 or 8 bytes of affected memory sections unavailable to avoid PC modifying instructions on these locations Remaining instructions or data can still be stored on these locations DMA4 DMA Module Category Functional Function Corrupted write access to 20 bit DMA registers De...

Page 14: ... all eUSCI_B modes SPI and I2C are affected Workaround 1 Use Interrupt Service Routines to transfer data to and from the eUSCI_A or eUSCI_B OR 2 When using DMA channel 0 for transferring data to and from the eUSCI_A or eUSCI_B use DMA channel 2 lower priority than DMA channel 0 to read the same register of the eUSCI_A or eUSCI_B that DMA channel 0 is working with Use the same USCI IFG e g UCA0RXIF...

Page 15: ...a breakpoint is hit or when the debug session is halted Workaround This erratum has been addressed in MSPDebugStack version 3 5 0 1 It is also available in released IDE EW430 IAR version 6 30 3 and CCS version 6 1 1 or newer If using an earlier version of either IDE or MSPDebugStack do not halt or use breakpoints during a DMA transfer Note This erratum applies to debug mode only EEM23 EEM Module C...

Page 16: ... as MSP430 DLL v3 4 3 4 OR b Roll back the debug stack by either performing a clean re installation of a previous version of the IDE or by manually replacing the debug stack with a prior version such as MSP430 DLL v3 4 3 4 that can be obtained from http www ti com tool MSPDS 2 In case JTAG connectivity fails during the LPMx 5 debug mode the device supply voltage level needs to be raised or lowered...

Page 17: ...ified Clock System Control 5 Register UCSCTL5 to divide MCLK by two prior to entering LPM3 or LPM4 set DIVMx 001 This prevents MCLK from running out of spec when the CPU wakes from the low power mode Following the wakeup fromthe low power mode wait 32 48 80 or 100 cycles for core voltage levels 0 1 2 and 3 respectively before resetting DIVM xto zero and running MCLK at full speed for example __del...

Page 18: ...y Functional Function Device may not wake up from LPM2 LPM3 or LPM4 Description Device may not wake up from LPM2 LPM3 or LMP4 if an interrupt occurs within 1 us after the entry to the specified LPMx entry can be caused either by user code or automatically for example after a previous ISR is completed Device can be recovered with an external reset or a power cycle Additionally a PUC can also be use...

Page 19: ...al mode Instead force the modules to remain ON even in LPMx Note that this will cause increased power consumption when in LPMx Refer to the MSP430 Driver Library MSPDRIVERLIB for proper PMM configuration functions Use the following function PMM15Check void to determine whether or not the existing PMM configuration is affected by the erratum The return value of the function is 1 if the configuratio...

Page 20: ...3 and LPM4 PMM20 PMM Module Category Functional Function Unexpected SVSL SVML event during wakeup from LPM2 3 4 in fast wakeup mode Description If PMM low side is configured to operate in fast wakeup mode during wakeup from LPM2 3 4 the internal VCORE voltage can experience voltage drop below the corresponding SVSL and SVML threshold recommendation according to User s Guide leading to an unexpecte...

Page 21: ... pin reset function after access to SVSMHCTL or SVSMLCTL To prevent lock up caused by use case 2 a timeout for the SVSMLDLYIFG flag check should be implemented to 300us PORT15 PORT Module Category Functional Function In system debugging causes the PMALOCKED bit to be always set Description The port mapping controller registers cannot be modified when single stepping or halting at break points betw...

Page 22: ...re off the tamper detection function triggered by RTCCAP0 and RTCCAP1 pins cannot get a correct time stamp value Workaround None SD3 SD Module Category Functional Function Incorrect conversion result in twos complement mode when VFS is applied Description When the SD converter is configured in twos complement mode with left or right alignment and any OSR setting applying the VFS voltage at the inp...

Page 23: ...er OFIFG clearing USCI36 USCI Module Category Functional Function UCLKI not usable in I2C master mode Description When EUSCIB is configured as I2C Master with the external UCLKI as clock source the UCLKI signal is not available and cannot be used to source I2C clock Workaround Use LFXTCLK via ACLK or HFXTCLK via SMCLK as clock source BRCLK for I2C in master mode with external clock source USCI37 U...

Page 24: ...ch byte in multi byte transmission Description UCTXCPTIFG flag is triggered at the last stop bit of every UART byte transmission independently of an empty buffer when transmitting multiple byte sequences via UART The erroneous UART behavior occurs with and without DMA transfer Workaround None USCI47 USCI Module Category Functional Function eUSCI SPI slave with clock phase UCCKPH 1 Description The ...

Page 25: ...pin master mode with UCSTEM 0 STE pin used as an input to prevent conflicts with other SPI masters data that is moved into UCxTXBUF while the UCxSTE input is in the inactive state may not be transmitted correctly If the eUSCI is used with UCSTEM 1 STE pin used to output an enable signal data is transmitted correctly Workaround When using the STE pin in conflict prevention mode UCSTEM 0 only move d...

Page 26: ...4 2019 to May 19 2021 Page Changed the document format and structure updated the numbering format for tables figures and cross references throughout the document 6 Revision History www ti com 26 MSP430F6749 Microcontroller SLAZ484AD DECEMBER 2012 REVISED MAY 2021 Submit Document Feedback Copyright 2021 Texas Instruments Incorporated ...

Page 27: ...s are subject to change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of these resources is prohibited No license is granted to any other TI intellectual property right or to any third party intellectual property right TI disclaims responsibility for and you wi...

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